| 國立臺灣大學 |
2004 |
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
|
Kuo, Chien-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB
|
Liu, Ming-Huang; Ou, Wei-Yang; Su, Tsung-Yi; Huang, Kuo-Chan; Liu, Shen-Iuan |
| 淡江大學 |
2003-12 |
A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator
|
Chang, Hsiang-hui; Kuo, Chien-hung; Liu, Ming-huang; Liu, Shen-Iuan |
| 淡江大學 |
2003-08 |
A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator
|
郭建宏; Kuo, Chien-hung; Kao, Tsung-kai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003-06 |
Selective metal parallel shunting inductor and its VCO application
|
Wu, Chia-Hsin; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003-06 |
Low jitter Butterworth delay-locked loops
|
Chang, Hsiang-Hui; Sun, Chih-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003-04 |
A Spread-Spectrum Clock Generator With Triangular Modulation
|
Chang, Hsiang-Hui; Hua, I-Hui; Liu, Shen-Iuan |
| 淡江大學 |
2003-02 |
CMOS Magnetic Field to Frequency Converter
|
Chen, Shr-lung; Kuo, Chien-hung; Liu, Shen-iuan |
| 國立臺灣大學 |
2003-01 |
CMOS exponential function generator
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
A fast locking and low jitter delay-locked loop using DHDL
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
CMOS magnetic field to frequency converter
|
Chen, Shr-Lung; Kuo, Chien-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
Analysis of on-chip spiral inductors using the distributed capacitance model
|
Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus
|
Chang, Hsiang-Hui; Dehng, Giang-Kaai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
CMOS Tunable 1/x Circuit and its Applications
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
A sub-1V fourth-order bandpass delta-sigma modulator
|
Chang, Hsiang-Hui; Kuo, Chien-Hung; Liu, Ming-Huang; Liu, Shen-Iuan |
| 淡江大學 |
2002-12 |
Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
|
Kuo, Chien-hung; Hsueh, Tzu-chien; Liu, Shen-iuan |
| 國立臺灣大學 |
2002-08 |
Analysis of on-chip spiral inductors using the distributed capacitance model
|
Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
A wide-range and fixed latency of one clock cycle delay-locked loop
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network
|
Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
Analysis and application of miniature 3D inductor
|
Wu, Chia-Hsin; Tang, Chih-Chun; Chiu, Chi-Kun; Liu, Shen-Iuan |
| 臺大學術典藏 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
|
Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei |
| 臺大學術典藏 |
2002-05 |
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network
|
Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan; Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan |
