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机构	日期	题名	作者
國立臺灣大學	2009	A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier	Chang, Jung-Yu; Fan, Che-Wei; Liang, Che-Fu; Liu, Shen-Iuan
國立臺灣大學	2009	A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology	Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan
國立臺灣大學	2009	Effects of Hydration Levels on the Bandwidth of Microwave Resonant Absorption Induced by Confined Acoustic Vibrations	Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang
臺大學術典藏	2009	Effects of Hydration Levels on the Bandwidth of Microwave Resonant Absorption Induced by Confined Acoustic Vibrations	Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang; Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang
臺大學術典藏	2009	A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3-μm LTPS-TFT Technology	Lin, Wei-Ming; Liu, Shen-Iuan; Kuo, Chun-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting; Lin, Wei-Ming; Liu, Shen-Iuan; Kuo, Chun-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting
國立臺灣大學	2008-10	A 3~8GHz delay-locked loop with cycle jitter calibration	Chuang, Chi-Nan; Liu, Shen-Iuan
國立臺灣大學	2008-07	A 81.5~85.9GHz injection-locked frequency divider in 65nm CMOS	Cho, Lan-Chou; Tsai, Kun-Hung; Hung, Chao-Ching; Liu, Shen-Iuan
國立臺灣大學	2008-03	40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS	Liao, Chih-Fan; Liu, Shen-Iuan
國立臺灣大學	2008-02	An all-digital fast-locking programmable DLL-based clock generator	Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan
國立臺灣大學	2008	A digital calibration technique for charge pumps in phase-locked systems	Liang, Che-Fu; Chen, Shin-Hua; Liu, Shen-Iuan
國立臺灣大學	2008	An All-Digital Fast-Locking Programmable DLL-Based Clock Generator	Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan
國立臺灣大學	2008	A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier	Wang, I-Hsin; Liu, Shen-Iuan
國立臺灣大學	2008	40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS	Liao, Chih-Fan; Liu, Shen-Iuan
國立臺灣大學	2008	A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector	Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan
國立臺灣大學	2008	A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS	Lee, Chihun; Cho, Lan-Chou; Wu, Jia-Hao; Liu, Shen-Iuan
國立臺灣大學	2008	A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration	Chuang, Chi-Nan; Liu, Shen-Iuan
國立臺灣大學	2008	10-Gb/s Inductorless CDRs With Digital Frequency Calibration	Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan
國立臺灣大學	2008	A delay-locked loop with statistical background calibration	Kao, Shao-Ku; Liu, Shen-Iuan
國立臺灣大學	2008	A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery	Liao, Chih-Fan; Liu, Shen-Iuan
國立臺灣大學	2008	An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line	Chen, Chao-Chyun; Liu, Shen-Iuan
國立臺灣大學	2008	Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs	Lin, Shao-Hung; Liu, Shen-Iuan
臺大學術典藏	2007-04-19T04:34:31Z	A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution	Chen, Poki;Liu, Shen-Iuan; Chen, Poki; Liu, Shen-Iuan
臺大學術典藏	2007-04-19T04:12:30Z	CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure	Wu, Yan-Pei; Chen, Jiann-Jong; Liu, Shen-Iuan; Tsay, Jiann-Horng; Tsay, Jiann-Horng; Liu, Shen-Iuan; Chen, Jiann-Jong; Wu, Yan-Pei
國立臺灣大學	2007	A time-constant calibrated phase-locked loop with a fast-locked time	Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan
國立臺灣大學	2007	A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm	Yang, Rong-Jyi; Liu, Shen-Iuan
國立臺灣大學	2007	A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS	Wang, I-Hsin; Liu, Shen-Iuan
國立臺灣大學	2007	An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS	Chen, Ke-Hou; Lu, Jian-Hao; Chen, Bo-Jiun; Liu, Shen-Iuan
國立臺灣大學	2007	A multi-band burst-mode clock and data recovery circuit	Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan
國立臺灣大學	2007	A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops	Chen, Chao-Chyun; Lee, Sheng-Chou; Liu, Shen-Iuan
國立臺灣大學	2007	A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology	Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan
國立臺灣大學	2007	A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop	Kao, Shao-Ku; Chen, Bo-Jiun; Liu, Shen-Iuan
國立臺灣大學	2007	Spur-suppression techniques for frequency synthesizers	Liang, Che-Fu; Chen, Hsin-Hua; Liu, Shen-Iuan
國立臺灣大學	2007	A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump	Chuang, Chi-Nan; Liu, Shen-Iuan
國立臺灣大學	2007	A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology	Yang, Rong-Jyi; Liu, Shen-Iuan
國立臺灣大學	2007	A DLL-based variable-phase clock buffer	Chen, Chao-Chyun; Chang, Jung-Yu; Liu, Shen-Iuan
淡江大學	2006-07	Magnetic-field-to-digital converter using PWM and TDC techniques	郭建宏; Kuo, Chien-hung; Chen, Shr-lung; Liu, Shen-iuan
國立臺灣大學	2006-02	CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique	Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan
國立臺灣大學	2006	A spur-reduction technique for a 5-GHz frequency synthesizer	Kuo, Chun-Yi; Chang, Jung-Yu; Liu, Shen-Iuan
國立臺灣大學	2006	A 1 V Phase Locked Loop with Leakage Compensation in 0.13 ?m CMOS Technology	CHUANG, Chi-Nan; LIU, Shen-Iuan
國立臺灣大學	2006	A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit	Yang, Rong-Jyi; Chao, Kuan-Hua; Liu, Shen-Iuan
國立臺灣大學	2006	A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop	Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan
國立臺灣大學	2006	A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit	Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan
國立臺灣大學	2006	All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles	Wang, You-Jen; Kao, Shao-Ku; Liu, Shen-Iuan
國立臺灣大學	2006	A Calibrated Pulse Generator for Impulse-Radio UWB Applications	Liang, Che-Fu; Liu, Shih-Tsai; Liu, Shen-Iuan
國立臺灣大學	2006	All-digital fast-locked synchronous duty cycle corrector	Kao, Shao-Ku; Liu, Shen-Iuan
國立臺灣大學	2005-09	A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver	Liao, Chih-Fan; Liu, Shen-Iuan
淡江大學	2005-05-23	A tunable bandpass ΔΣ modulator using double sampling	郭建宏; Kuo, Chien-hung; Chen, Chang-hung; Huang, Shih-lin; Liu, Shen-iuan
國立臺灣大學	2005-05	A 15mW 69dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications	Lee, Hua-Chin; Lin, Chien-Chih; Wu, Chia-Hsin; Liu, Shen-Iuan; Wang, Chorng-Kuang; Tsao, Hen-Wai
國立臺灣大學	2005-03	A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop	Chang, Hsiang-Hui; Liu, Shen-Iuan
國立臺灣大學	2005-03	CMOS Current-Mode Divider and Its Applications	Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken

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