| 國立臺灣大學 |
2009 |
A leakage-compensated PLL in 65nm CMOS technology
|
Hung, Chao-Ching; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
An 8-bit 20MS/s ZCBC time-domain analog-to-digital data converter
|
Wang, I-Hsin; Lee, Hwei-Yu; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider
|
Lee, I-Ting; Tsai, Kun-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS technology
|
Cho, Lan-Chou; Lee, Chihun; Hung, Chao-Ching; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3-μm LTPS-TFT Technology
|
Lin, Wei-Ming; Liu, Shen-Iuan; Kuo, Chun-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting |
| 國立臺灣大學 |
2009 |
A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier
|
Chang, Jung-Yu; Fan, Che-Wei; Liang, Che-Fu; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology
|
Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan |
| 國立臺灣大學 |
2009 |
Effects of Hydration Levels on the Bandwidth of Microwave Resonant Absorption Induced by Confined Acoustic Vibrations
|
Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang |
| 臺大學術典藏 |
2009 |
Effects of Hydration Levels on the Bandwidth of Microwave Resonant Absorption Induced by Confined Acoustic Vibrations
|
Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang; Liu, Tzu-Ming; Chen, Hung-Pin; Yeh, Shih-Chia; Wu, Chih-Yu; Wang, Chung-Hsiung; Luo, Tang-Nian; Chen, Yi-Jan; Liu, Shen-Iuan; Sun, Chi-Kuang |
| 臺大學術典藏 |
2009 |
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3-μm LTPS-TFT Technology
|
Lin, Wei-Ming; Liu, Shen-Iuan; Kuo, Chun-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting; Lin, Wei-Ming; Liu, Shen-Iuan; Kuo, Chun-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting |
| 國立臺灣大學 |
2008-10 |
A 3~8GHz delay-locked loop with cycle jitter calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-07 |
A 81.5~85.9GHz injection-locked frequency divider in 65nm CMOS
|
Cho, Lan-Chou; Tsai, Kun-Hung; Hung, Chao-Ching; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-03 |
40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-02 |
An all-digital fast-locking programmable DLL-based clock generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A digital calibration technique for charge pumps in phase-locked systems
|
Liang, Che-Fu; Chen, Shin-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
|
Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS
|
Lee, Chihun; Cho, Lan-Chou; Wu, Jia-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
|
Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A delay-locked loop with statistical background calibration
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line
|
Chen, Chao-Chyun; Liu, Shen-Iuan |
