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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"liu shen iuan"的相關文件
顯示項目 91-100 / 185 (共19頁)
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| 國立臺灣大學 |
2004-02 |
A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet
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Wu, Chia-Hsin; Liu, Chang-Shun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low-voltage CMOS voltage-mode divider and its application
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low voltage and low power CMOS exponential-control variable-gain amplifier
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A Mixed-mode Synchronous Mirror Delay Insensitive to Supply and Load Variations
|
Sun, Chih-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators
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Kuo, Chien-Hung; Chen, Shr-Lung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC
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Liu, Ming-Huang; Huang, Kuo-Chan; Ou, Wei-Yang; Su, Tsung-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low-voltage and low-power CMOS voltage-to-current converter
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet
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Yang, Rong-Jyi; Chen, Shang-Ping; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection
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Chang, Hsiang-Hui; Yang, Rong-Jyi; Liu, Shen-Iuan |
顯示項目 91-100 / 185 (共19頁)
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每頁顯示[10|25|50]項目
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