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Showing items 116-125 of 185  (19 Page(s) Totally)
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Institution Date Title Author
淡江大學 2002-12 Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm Kuo, Chien-hung; Hsueh, Tzu-chien; Liu, Shen-iuan
國立臺灣大學 2002-08 Analysis of on-chip spiral inductors using the distributed capacitance model Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan
國立臺灣大學 2002-08 A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan
臺大學術典藏 2002-08 A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan
國立臺灣大學 2002-05 A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan
國立臺灣大學 2002-05 A wide-range and fixed latency of one clock cycle delay-locked loop Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan
國立臺灣大學 2002-05 CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan
國立臺灣大學 2002-05 Analysis and application of miniature 3D inductor Wu, Chia-Hsin; Tang, Chih-Chun; Chiu, Chi-Kun; Liu, Shen-Iuan
臺大學術典藏 2002-05 A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei
臺大學術典藏 2002-05 CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan; Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan

Showing items 116-125 of 185  (19 Page(s) Totally)
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