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"liu shen iuan"的相关文件
显示项目 46-55 / 185 (共19页)
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| 國立臺灣大學 |
2008 |
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
|
Lin, Shao-Hung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:34:31Z |
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
|
Chen, Poki;Liu, Shen-Iuan; Chen, Poki; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:12:30Z |
CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
|
Wu, Yan-Pei; Chen, Jiann-Jong; Liu, Shen-Iuan; Tsay, Jiann-Horng; Tsay, Jiann-Horng; Liu, Shen-Iuan; Chen, Jiann-Jong; Wu, Yan-Pei |
| 國立臺灣大學 |
2007 |
A time-constant calibrated phase-locked loop with a fast-locked time
|
Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS
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Chen, Ke-Hou; Lu, Jian-Hao; Chen, Bo-Jiun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A multi-band burst-mode clock and data recovery circuit
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Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops
|
Chen, Chao-Chyun; Lee, Sheng-Chou; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology
|
Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan |
显示项目 46-55 / 185 (共19页)
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