| 國立臺灣大學 |
2006 |
A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop
|
Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles
|
Wang, You-Jen; Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A Calibrated Pulse Generator for Impulse-Radio UWB Applications
|
Liang, Che-Fu; Liu, Shih-Tsai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
All-digital fast-locked synchronous duty cycle corrector
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005-09 |
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 淡江大學 |
2005-05-23 |
A tunable bandpass ΔΣ modulator using double sampling
|
郭建宏; Kuo, Chien-hung; Chen, Chang-hung; Huang, Shih-lin; Liu, Shen-iuan |
| 國立臺灣大學 |
2005-05 |
A 15mW 69dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications
|
Lee, Hua-Chin; Lin, Chien-Chih; Wu, Chia-Hsin; Liu, Shen-Iuan; Wang, Chorng-Kuang; Tsao, Hen-Wai |
| 國立臺灣大學 |
2005-03 |
A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop
|
Chang, Hsiang-Hui; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005-03 |
CMOS Current-Mode Divider and Its Applications
|
Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken |
| 臺大學術典藏 |
2005-03 |
CMOS Current-Mode Divider and Its Applications
|
Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
CMOS wideband amplifiers using multiple inductive-series peaking technique
|
Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A single-path pulsewidth control loop with a built-in delay-locked loop
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A wide-range multiphase delay-locked loop using mixed-mode VCDLs
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
Selective metal parallel shunting inductor and its VCO application
|
Wu, Chia-Hsin; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
CMOS Differential-Mode Exponential Voltage-To-Current Converter
|
Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken |
| 淡江大學 |
2004-11 |
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
|
郭建宏; Kuo, Chien-hung; Liu, Shen-iuan |
| 國立臺灣大學 |
2004-08 |
A low power 5Gb/s transimpedance amplifier with dual feedback technique
|
Wang, I-Hsin; Liu, Chung-Shun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-08 |
A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier
|
Lee, Chihun; Wu, Chia-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-05 |
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors
|
Wu, Chia-Hsin; Liao, Jieh-Wei; Liu, Shen-Iuan |
| 淡江大學 |
2004-04 |
Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators
|
郭建宏; Kuo, Chien-hung; Chen Shr-lung; Liu Shen-iuan |
| 國立臺灣大學 |
2004-03 |
A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2004-03 |
A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle
|
Han, Sung-Rung; Liu, Shen-Iuan; Han, Sung-Rung; Liu, Shen-Iuan |
