|
"liu wei chang"的相关文件
显示项目 1-10 / 27 (共3页)
1 2 3 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2019-04-02T06:04:52Z |
Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation
|
Chan, Ching-Da; Liu, Wei-Chang; Yang, Chia-Hsiang; Jou, Shyh-Jye |
| 國立交通大學 |
2019-04-02T06:04:27Z |
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems
|
Ng, Chee-Kit; Lin, Yu-Chun; Liu, Wei-Chang; Wu, Chin-Feng; Lou, Shyh-Lye |
| 國立交通大學 |
2018-08-21T05:54:19Z |
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
|
Liu, Chun-Yi; Sie, Meng-Siou; Leong, Edmund Wen Jen; Yao, Yu-Cheng; Lopez, Henry; Jen, Chih-Wei; Liu, Wei-Chang; Jou, Shyh-Jye |
| 國立交通大學 |
2018-08-21T05:53:54Z |
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel
|
Liu, Chun-Yi; Sie, Meng-Siou; Leong, Edmund Wen Jen; Yao, Yu-Cheng; Jen, Chih-Wei; Liu, Wei-Chang; Wu, Chih-Feng; Jou, Shyh-Jye |
| 國立交通大學 |
2017-04-21T06:55:53Z |
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver
|
Wu, Chih-Feng; Liu, Wei-Chang; Tsui, Chia-Chun; Liu, Chun-Yi; Sie, Meng-Siou; Jou, Shyh-Jye (Jerry) |
| 國立交通大學 |
2017-04-21T06:50:09Z |
A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
|
Davila, Henry Lopez; Liu, Chun-Yi; Liu, Wei-Chang; Huang, Shen-Jui; Jou, Shyh-Jye; Chen, Sau-Gee |
| 國立交通大學 |
2017-04-21T06:49:42Z |
Low power and power aware design for DVB-T/H baseband inner receiver
|
Tseng, Chi-Yao; Wei, Ting-Chen; Liu, Wei-Chang; Jon, Shyh-Jye |
| 國立交通大學 |
2017-04-21T06:49:27Z |
Gb/s Prototyping of 60GHz Indoor Wireless SC/OFDM Transmitter and Receiver on FPGA Demo System
|
Arya, Pranav; Huang, Liang-Yu; Liu, Wei-Chang; Chang, Hsin-Ting; Jen, Chih-Wei; Wu, Chi-Feng; Jou, Shy-Jye |
| 國立交通大學 |
2017-04-21T06:49:00Z |
ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
|
Liu, Wei-Chang; Chan, Ching-Da; Huang, Shuo-An; Lo, Chi-Wei; Yang, Chia-Hsiang; Jou, Shyh-Jye |
| 國立交通大學 |
2017-04-21T06:48:54Z |
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
|
Liu, Chun-Yi; Sie, Meng-Siou; Leong, Edmund Wen Jen; Yao, Yu-Cheng; Lopez, Henry; Jen, Chih-Wei; Liu, Wei-Chang; Jou, Shyh-Jye |
显示项目 1-10 / 27 (共3页)
1 2 3 > >>
每页显示[10|25|50]项目
|
