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"lo kai yu"
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| 國立交通大學 |
2019-04-03T06:40:10Z |
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
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Chang, Chia-Wen; Lo, Kai-Yu; Ibrahim, Hossameldin A.; Su, Ming-Chiuan; Chu, Yuan-Hua; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-12T02:37:58Z |
一個3GHz具隨機取樣突波抑制技術之全數位式鎖相迴路
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羅凱俞; Lo, Kai-Yu; 周世傑; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:33:44Z |
A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
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Wang, Li-Rong; Lo, Kai-Yu; Jou, Shyh-Jye |
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