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"lo yu lung"的相關文件
顯示項目 11-20 / 168 (共17頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目
| 朝陽科技大學 |
2019-11 |
Special Issue of The 13th International Conference on Advanced Information Technologies (AIT 2019) Categorization of Alpha Wave Music by SOM Reduction
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Lo, Yu-Lung;Deng, Yi-Lan |
| 國立成功大學 |
2019-09-26 |
積層製造系統與方法及特徵擷取方法
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楊浩青;YANG, HAW CHING;羅裕龍;LO, YU LUNG;蕭宏章;HSIAO, HUNG CHANG;王士豪;WANG, SHYH HAU;胡敏君;HU, MIN CHUN;黃熾宏;HUANG, CHIH HUNG;鄭芳田;CHENG, FAN TIEN |
| 淡江大學 |
2019-02-22 |
A Fast Transient Response and High Current Efficiency Output-Capacitorless Low Dropout Regulator for Low-Power SoC Applications
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Yang, Wei-Bin;Li, Yu-Hsin;Yu, Cheng-Yang;Lo, Yu-Lung |
| 朝陽科技大學 |
2018-12-31 |
A Study on Characterization of Alpha Wave Music
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羅有隆;鄧伊蘭; Lo, Yu-Lung;Deng, Yi-Lan |
| 國立成功大學 |
2018-01-04 |
Method and system for sensing glucose concentration
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Lo, Yu-Lung;Phan, Quoc-Hung;Liao, Chia-Chi |
| 淡江大學 |
2018 |
A current-controlled oscillator with temperature, voltage, and process compensation
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Yang, Wei-Bin;Chiang, Jen-Shiun;Cheng, Ching-Tsan;Wang, Chi-Hsiung;Shih, Horng-Yuan;Syu, Jia-Liang;Chen, Cing-Huan;Lo, Yu-Lung |
| 淡江大學 |
2017年10月 |
All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
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Tsai, Chih-Wei;Lo, Yu-Lung;Chang, Chia-Chen;Liu, Han-Ying;Yang, Wei-Bin;Cheng, Kuo-Hsing |
| 淡江大學 |
2017年10月 |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input
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Yang, Wei‑Bin;Lin, Yu-Yao;Lo, Yu-Lung |
| 淡江大學 |
2017年10月 |
A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
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Lo, Yu-Lung;Yang, Wei-Bin;Wang, Han-Hsien;Chen, Cing-Huan;Huang, Zi-Ang |
| 淡江大學 |
2017年10月 |
Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage
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Yang, Wei-Bin;Lo, Yu-Lung;Chang, Kuo-Ning;Lin, Yu-Yao |
顯示項目 11-20 / 168 (共17頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目
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