|
|
???tair.name??? >
???browser.page.title.author???
|
"lou j h"???jsp.browse.items-by-author.description???
Showing items 1-14 of 14 (1 Page(s) Totally)
1
View [10|25|50] records per page
| 國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
|
Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit
|
Lou, J. H.; Kuo, J. B. |
| 國立臺灣大學 |
1998-09 |
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder
|
Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1997-08 |
A 1.5 V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
|
Yeh, C.C.; Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1997-08 |
A 1.5 V bootstrapped pass-transistor-based carry look-ahead circuit suitable for low-voltage CMOS VLSI
|
Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1997-07 |
1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications
|
Yeh, C.C.; Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
|
Kuo, J.B.; Lou, J.H.; Su, K.W. |
| 臺大學術典藏 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
|
Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB |
| 國立臺灣大學 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
|
Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
| 國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 國立臺灣大學 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
|
Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
|
KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
Showing items 1-14 of 14 (1 Page(s) Totally)
1
View [10|25|50] records per page
|
