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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:04:43Z |
Using power gating techniques in area-array SoC floorplan design
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Yeh, Chi-Yi; Chen, Hung-Ming; Huang, Li-Da; Wei, Wei-Ting; Lu, Chao-Hung; Liu, Chien-Nan |
| 國立交通大學 |
2017-04-21T06:49:40Z |
Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu |
| 國立交通大學 |
2017-04-21T06:49:07Z |
On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy |
| 國立交通大學 |
2014-12-08T15:38:08Z |
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy |
| 國立交通大學 |
2014-12-08T15:31:26Z |
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu |
| 國立交通大學 |
2014-12-08T15:11:01Z |
Effective Decap Insertion in Area-Array SoC Floorplan Design
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy |
| 國立交通大學 |
2014-12-08T15:01:12Z |
An effective decap insertion method considering power supply noise during floorplanning
|
Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy |
Showing items 1-7 of 7 (1 Page(s) Totally)
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