|
English
|
正體中文
|
简体中文
|
总笔数 :2819103
|
|
造访人次 :
28457562
在线人数 :
682
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"lu liang ying"的相关文件
显示项目 1-10 / 10 (共1页)
1
每页显示[10|25|50]项目
| 國立成功大學 |
2022-06-21 |
使用結構方程分析台灣特殊需求兒童主要照顧者的健康決定因子
|
陸靚瀅; Lu, Liang-Ying |
| 國立成功大學 |
2018-12 |
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis
|
邱瀝毅; CHIOU, LIH-YIH;Lu, Liang-Ying |
| 國立成功大學 |
2018-10 |
Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level
|
邱瀝毅; CHIOU, LIH-YIH;Lu, Liang-Ying;Hsieh, Tsung-Yu;Weng, Pei-En |
| 國立成功大學 |
2017-08 |
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits
|
邱瀝毅; CHIOU, LIH-YIH;Lu, Liang-Ying |
| 國立成功大學 |
2016-01-08 |
Thermal simulation device and method for integrated circuits
|
Chiou, Lih-Yih;Lu, Liang-Ying |
| 國立彰化師範大學 |
2010-08 |
Peak Current Reduction Using an MTCMOS Technique
|
Lu, Liang-Ying; Wu, Tsung-Yi; Chiou, Lih-Yih; Shi, Jing-Wen |
| 國立成功大學 |
2009-04 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi; Lu, Liang-Ying |
| 國立彰化師範大學 |
2009 |
Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
|
Wu, Tsung-Yi ; Lu, Liang-Ying |
| 國立彰化師範大學 |
2008-12 |
Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates
|
Wu, Tsung-Yi; Lu, Liang-Ying; Liang, Cheng-Hsun |
| 國立彰化師範大學 |
2008-03 |
IR Drop Reduction Via a Flip-Flop Resynthesis Technique
|
Wu, Jiun-Kuan; Wu, Tsung-Yi; Lu, Liang-Ying; Chen, Kuang-Yao |
显示项目 1-10 / 10 (共1页)
1
每页显示[10|25|50]项目
|
