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"lu s k"
Showing items 11-20 of 70 (7 Page(s) Totally)
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| 國立臺灣科技大學 |
2018 |
A design for testability of open defects at interconnects in 3D stacked ICs
|
Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z. |
| 國立臺灣科技大學 |
2018 |
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories
|
Lu S.-K.; Jheng H.-C.; Lin H.-W.; Hashizume M. |
| 國立臺灣科技大學 |
2018 |
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories
|
Lu S.-K.; Zhong S.-X.; Hashizume M. |
| 國立臺灣科技大學 |
2018 |
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type
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Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume
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Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs
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Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K. |
| 國立臺灣科技大學 |
2018 |
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory
|
Lu S.-K.; Li H.-P.; Miyase K. |
| 國立臺灣科技大學 |
2018 |
Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories
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Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H. |
| 國立臺灣科技大學 |
2018 |
Progressive ECC Techniques for Phase Change Memory
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Lu, S.-K.;Li, H.-P.;Miyase, K. |
| 國立臺灣科技大學 |
2017 |
Online slack-Time binning for IO-registered die-To-die interconnects
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Zheng, C.-C;Huang, S.-Y;Lu, S.-K;Wang, T.-C;Tsai, K.-H;Cheng, W.-T. |
Showing items 11-20 of 70 (7 Page(s) Totally)
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