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"lu s k"
Showing items 36-45 of 70 (7 Page(s) Totally) << < 1 2 3 4 5 6 7 > >> View [10|25|50] records per page
| 國立臺灣科技大學 |
2016 |
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories
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Lu, S.-K;Zhong, S.-X;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories
|
Lu, S.-K;Lin, H.-W;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Address scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs
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Lu, S.-K.;Li, T.-L.;Hashizume, M.;Chen, J.-L. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs by injected charge volume
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Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs
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Lu, S.-K.;Lin, S.-L.;Lin, H.-W.;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit
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Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
A testable design for electrical interconnect tests of 3D ICs
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Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories
|
Lu, S.-K;Lin, H.-W;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs without boundary scan flip flops
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Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2014 |
A power saving mechanism for multimedia streaming services in cloud computing
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Ma, Y.-W.;Chen, J.-L.;Chou, C.-H.;Lu, S.-K. |
Showing items 36-45 of 70 (7 Page(s) Totally) << < 1 2 3 4 5 6 7 > >> View [10|25|50] records per page
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