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机构	日期	题名	作者
臺大學術典藏	2020-06-11T06:44:36Z	Integrated heterogeneous infrastructure for indoor positioning	Ma, Y.-W.;Chen, J.-L.;Tsai, Y.-H.;Chou, P.-C.;Lu, S.-K.;Kuo, S.-Y.; Ma, Y.-W.; Chen, J.-L.; Tsai, Y.-H.; Chou, P.-C.; Lu, S.-K.; Kuo, S.-Y.; SY-YEN KUO
國立臺灣科技大學	2020	Temperature Sensing with a Relaxation Oscillator in CMOS ICs	Sako, F.;Ikiri, Y.;Hashizume, M.;Yotsuyanagi, H.;Yokoyama, H.;Lu, S.-K.
國立臺灣科技大學	2020	Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards	Kanda, M.;Hashizume, M.;Ali, F.A.B.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2020	Fault-Aware Dependability Enhancement Techniques for Flash Memories	Lu, S.-K.;Yu, S.-C.;Hsu, C.-L.;Sun, C.-T.;Hashizume, M.;Yotsuyanagi, H.
國立臺灣科技大學	2020	Temperature Sensing with a Relaxation Oscillator in CMOS ICs	Sako, F.;Ikiri, Y.;Hashizume, M.;Yotsuyanagi, H.;Yokoyama, H.;Lu, S.-K.
國立臺灣科技大學	2019	Resistive open defect detection in SoCs by a test method based on injected charge volume after test input application	Matsumoto, Y.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2019	Stand-by mode test method of interconnects between dies in 3d ICs with IEEE 1149.1 test circuits	Kanda, M.;Yabui, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2019	Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM	Lu, S.-K.;Huang, Huang H.-K.;Hsu, C.-L.;Sun, C.-T.;Miyase, K.
國立臺灣科技大學	2019	A fault-tolerant MPSoC for CubeSats	Fuchs, C.M.;Chou, P.;Wen, X.;Murillo, N.M.;Furano, G.;Holst, S.;Tavoularis, A.;Lu, S.-K.;Plaat, A.;Marinis, K.
國立臺灣科技大學	2019	A static method for analyzing hotspot distribution on the LSI	Miyase, K.;Kawano, Y.;Lu, S.-K.;Wen, X.;Kajihara, S.
國立臺灣科技大學	2018	A design for testability of open defects at interconnects in 3D stacked ICs	Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z.
國立臺灣科技大學	2018	Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories	Lu S.-K.; Jheng H.-C.; Lin H.-W.; Hashizume M.
國立臺灣科技大學	2018	Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories	Lu S.-K.; Zhong S.-X.; Hashizume M.
國立臺灣科技大學	2018	A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type	Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2018	A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume	Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2018	Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs	Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K.
國立臺灣科技大學	2018	Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory	Lu S.-K.; Li H.-P.; Miyase K.
國立臺灣科技大學	2018	Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories	Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H.
國立臺灣科技大學	2018	Progressive ECC Techniques for Phase Change Memory	Lu, S.-K.;Li, H.-P.;Miyase, K.
國立臺灣科技大學	2017	Online slack-Time binning for IO-registered die-To-die interconnects	Zheng, C.-C;Huang, S.-Y;Lu, S.-K;Wang, T.-C;Tsai, K.-H;Cheng, W.-T.
國立臺灣科技大學	2017	Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power	Lu, S.-K.;Huang, Huang H.-K.
國立臺灣科技大學	2017	Electrical tests for capacitive open defects in assembled PCBs	Alia, F.A.B.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2017	Electrical test of resistive and capacitive open defects at data bus in 3D memory IC	Hashizume, M.;Shiraishi, Y.;Yotsuyanagi, H.;Yokoyama, H.;Tada, Tada T.;Lu, S.-K.
國立臺灣科技大學	2017	Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs	Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2017	A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs	Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2016	A Framework for Third Party Android Marketplaces to Identify Repackaged Apps	Lo, N.-W;Lu, S.-K;Chuang, Y.-H.
國立臺灣科技大學	2016	Integrated heterogeneous infrastructure for indoor positioning	Ma, Y.-W;Chen, J.-L;Tsai, Y.-H;Chou, P.-C;Lu, S.-K;Kuo, S.-Y.
國立臺灣科技大學	2016	Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories	Lu, S.-K;Tsai, C.-J;Hashizume, M.
國立臺灣科技大學	2016	A built-in electrical test circuit for detecting open leads in assembled PCB circuits	Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z.
國立臺灣科技大學	2016	Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit	Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學	2016	Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories	Lu, S.-K;Tsai, C.-J;Hashizume, M.
國立臺灣科技大學	2016	A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs	Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z.
國立臺灣科技大學	2016	A power supply circuit for interconnect tests based on injected charge volume of 3D IC	Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學	2016	A built-in defective level monitor of resistive open defects in 3D ICs with logic gates	Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學	2016	Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops	Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學	2016	Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories	Lu, S.-K;Zhong, S.-X;Hashizume, M.
國立臺灣科技大學	2016	An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories	Lu, S.-K;Lin, H.-W;Hashizume, M.
國立臺灣科技大學	2015	Address scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs	Lu, S.-K.;Li, T.-L.;Hashizume, M.;Chen, J.-L.
國立臺灣科技大學	2015	Electrical interconnect test method of 3D ICs by injected charge volume	Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2015	Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs	Lu, S.-K.;Lin, S.-L.;Lin, H.-W.;Hashizume, M.
國立臺灣科技大學	2015	Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit	Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學	2015	A testable design for electrical interconnect tests of 3D ICs	Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K.
國立臺灣科技大學	2015	An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories	Lu, S.-K;Lin, H.-W;Hashizume, M.
國立臺灣科技大學	2015	Electrical interconnect test method of 3D ICs without boundary scan flip flops	Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學	2014	A power saving mechanism for multimedia streaming services in cloud computing	Ma, Y.-W.;Chen, J.-L.;Chou, C.-H.;Lu, S.-K.
國立臺灣科技大學	2013	Testable design for electrical testing of open defects at interconnects in 3D ICs	Hashizume, M.;Konishi, T.;Yotsuyanag, H.;Lu, S.-K.
國立臺灣科技大學	2013	Error-tolerance evaluation and design techniques for motion estimation computing arrays	Lu, S.-K.;Chen, M.-C.;Chen, Y.-C.
國立臺灣科技大學	2013	Efficient test and repair architectures for 3D TSV-based random access memories	Lu, S.-K.;Lu, U.-C.;Pong, S.-W.;Cheng, H.-C.
國立臺灣科技大學	2013	Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC	Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z.
國立臺灣科技大學	2013	Built-in IDDT appearance time sensor for detecting open faults in 3D IC	Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.

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