| 國立臺灣科技大學 |
2018 |
Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs
|
Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K. |
| 國立臺灣科技大學 |
2018 |
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory
|
Lu S.-K.; Li H.-P.; Miyase K. |
| 國立臺灣科技大學 |
2018 |
Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories
|
Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H. |
| 國立臺灣科技大學 |
2018 |
Progressive ECC Techniques for Phase Change Memory
|
Lu, S.-K.;Li, H.-P.;Miyase, K. |
| 國立臺灣科技大學 |
2017 |
Online slack-Time binning for IO-registered die-To-die interconnects
|
Zheng, C.-C;Huang, S.-Y;Lu, S.-K;Wang, T.-C;Tsai, K.-H;Cheng, W.-T. |
| 國立臺灣科技大學 |
2017 |
Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power
|
Lu, S.-K.;Huang, Huang H.-K. |
| 國立臺灣科技大學 |
2017 |
Electrical tests for capacitive open defects in assembled PCBs
|
Alia, F.A.B.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Electrical test of resistive and capacitive open defects at data bus in 3D memory IC
|
Hashizume, M.;Shiraishi, Y.;Yotsuyanagi, H.;Yokoyama, H.;Tada, Tada T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs
|
Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs
|
Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A Framework for Third Party Android Marketplaces to Identify Repackaged Apps
|
Lo, N.-W;Lu, S.-K;Chuang, Y.-H. |
| 國立臺灣科技大學 |
2016 |
Integrated heterogeneous infrastructure for indoor positioning
|
Ma, Y.-W;Chen, J.-L;Tsai, Y.-H;Chou, P.-C;Lu, S.-K;Kuo, S.-Y. |
| 國立臺灣科技大學 |
2016 |
Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories
|
Lu, S.-K;Tsai, C.-J;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
A built-in electrical test circuit for detecting open leads in assembled PCB circuits
|
Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit
|
Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
|
Lu, S.-K;Tsai, C.-J;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs
|
Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
A power supply circuit for interconnect tests based on injected charge volume of 3D IC
|
Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in defective level monitor of resistive open defects in 3D ICs with logic gates
|
Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops
|
Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories
|
Lu, S.-K;Zhong, S.-X;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories
|
Lu, S.-K;Lin, H.-W;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Address scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs
|
Lu, S.-K.;Li, T.-L.;Hashizume, M.;Chen, J.-L. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs by injected charge volume
|
Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs
|
Lu, S.-K.;Lin, S.-L.;Lin, H.-W.;Hashizume, M. |
