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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Showing items 26-50 of 70  (3 Page(s) Totally)
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Institution Date Title Author
國立臺灣科技大學 2016 A Framework for Third Party Android Marketplaces to Identify Repackaged Apps Lo, N.-W;Lu, S.-K;Chuang, Y.-H.
國立臺灣科技大學 2016 Integrated heterogeneous infrastructure for indoor positioning Ma, Y.-W;Chen, J.-L;Tsai, Y.-H;Chou, P.-C;Lu, S.-K;Kuo, S.-Y.
國立臺灣科技大學 2016 Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories Lu, S.-K;Tsai, C.-J;Hashizume, M.
國立臺灣科技大學 2016 A built-in electrical test circuit for detecting open leads in assembled PCB circuits Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z.
國立臺灣科技大學 2016 Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學 2016 Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories Lu, S.-K;Tsai, C.-J;Hashizume, M.
國立臺灣科技大學 2016 A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z.
國立臺灣科技大學 2016 A power supply circuit for interconnect tests based on injected charge volume of 3D IC Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學 2016 A built-in defective level monitor of resistive open defects in 3D ICs with logic gates Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學 2016 Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學 2016 Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories Lu, S.-K;Zhong, S.-X;Hashizume, M.
國立臺灣科技大學 2016 An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories Lu, S.-K;Lin, H.-W;Hashizume, M.
國立臺灣科技大學 2015 Address scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs Lu, S.-K.;Li, T.-L.;Hashizume, M.;Chen, J.-L.
國立臺灣科技大學 2015 Electrical interconnect test method of 3D ICs by injected charge volume Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2015 Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs Lu, S.-K.;Lin, S.-L.;Lin, H.-W.;Hashizume, M.
國立臺灣科技大學 2015 Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2015 A testable design for electrical interconnect tests of 3D ICs Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K.
國立臺灣科技大學 2015 An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories Lu, S.-K;Lin, H.-W;Hashizume, M.
國立臺灣科技大學 2015 Electrical interconnect test method of 3D ICs without boundary scan flip flops Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K.
國立臺灣科技大學 2014 A power saving mechanism for multimedia streaming services in cloud computing Ma, Y.-W.;Chen, J.-L.;Chou, C.-H.;Lu, S.-K.
國立臺灣科技大學 2013 Testable design for electrical testing of open defects at interconnects in 3D ICs Hashizume, M.;Konishi, T.;Yotsuyanag, H.;Lu, S.-K.
國立臺灣科技大學 2013 Error-tolerance evaluation and design techniques for motion estimation computing arrays Lu, S.-K.;Chen, M.-C.;Chen, Y.-C.
國立臺灣科技大學 2013 Efficient test and repair architectures for 3D TSV-based random access memories Lu, S.-K.;Lu, U.-C.;Pong, S.-W.;Cheng, H.-C.
國立臺灣科技大學 2013 Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z.
國立臺灣科技大學 2013 Built-in IDDT appearance time sensor for detecting open faults in 3D IC Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.

Showing items 26-50 of 70  (3 Page(s) Totally)
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