臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:42:27Z	Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces	H.-H. Chuang;C.-J. Hsu;M.-Z. Hong;D. Hsu;R. Huang;L.-C. Hsiao;T.-L. Wu; H.-H. Chuang; C.-J. Hsu; M.-Z. Hong; D. Hsu; R. Huang; L.-C. Hsiao; T.-L. Wu; TZONG-LIN WU
臺大學術典藏	2018-09-10T07:42:27Z	Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces	H.-H. Chuang;C.-J. Hsu;M.-Z. Hong;D. Hsu;R. Huang;L.-C. Hsiao;T.-L. Wu; H.-H. Chuang; C.-J. Hsu; M.-Z. Hong; D. Hsu; R. Huang; L.-C. Hsiao; T.-L. Wu; TZONG-LIN WU
臺大學術典藏	2018-09-10T07:08:57Z	Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory	H.-H. Chuang; S.-J. Wu; M.-Z. Hong; D. Hsu; R. Huang; T.-L. Wu; TZONG-LIN WU; H.-H. Chuang;S.-J. Wu;M.-Z. Hong;D. Hsu;R. Huang;T.-L. Wu
臺大學術典藏	2018-09-10T07:08:57Z	Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory	H.-H. Chuang; S.-J. Wu; M.-Z. Hong; D. Hsu; R. Huang; T.-L. Wu; TZONG-LIN WU; H.-H. Chuang;S.-J. Wu;M.-Z. Hong;D. Hsu;R. Huang;T.-L. Wu

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