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Showing items 1-4 of 4 (1 Page(s) Totally) 1 View [10|25|50] records per page
國立交通大學 |
2019-04-02T06:00:02Z |
A CMOS mismatch model and scaling effects
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Wong, SC; Pan, KH; Ma, DJ |
國立交通大學 |
2014-12-08T15:45:44Z |
Modeling of interconnect capacitance, delay, and crosstalk in VLSI
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Wong, SC; Lee, GY; Ma, DJ |
國立交通大學 |
2014-12-08T15:45:20Z |
An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
|
Wong, SC; Lee, TGY; Ma, DJ; Chao, CJ |
國立交通大學 |
2014-12-08T15:01:44Z |
A CMOS mismatch model and scaling effects
|
Wong, SC; Pan, KH; Ma, DJ |
Showing items 1-4 of 4 (1 Page(s) Totally) 1 View [10|25|50] records per page
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