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"ma g h"的相關文件
顯示項目 1-13 / 13 (共1頁)
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| 國立交通大學 |
2017-04-21T06:49:08Z |
Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineering
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Mao, A. Y.; Lin, W. M.; Yang, Cw.; Hsieh, Y. S.; Cheng, L. W.; Lee, G. D.; Tsai, C. T.; Chung, S. S.; Ma, G. H. |
| 國立交通大學 |
2014-12-08T15:48:25Z |
The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
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Hsieh, E. R.; Chang, Derrick W.; Chung, S. S.; Lin, Y. H.; Tsai, C. H.; Tsai, C. T.; Ma, G. H. |
| 國立交通大學 |
2014-12-08T15:48:21Z |
New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond
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Hsieh, E. R.; Chung, Steve S.; Lin, Y. H.; Tsai, C. H.; Liu, P. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:45:54Z |
The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) Approach
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Chang, C. M.; Chung, Steve S.; Hsieh, Y. S.; Cheng, L. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:45:53Z |
More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability
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Chung, Steve S.; Hsieh, E. R.; Huang, D. C.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:39:25Z |
The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond
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Lin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H. |
| 國立交通大學 |
2014-12-08T15:24:59Z |
Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm
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Lee, G. D.; Chung, S. S.; Mao, A. Y.; Lin, W. M.; Yang, C. W.; Hsieh, Y. S.; Chu, K. T.; Cheng, L. W.; Tai, H.; Hsu, L. T.; Lee, C. R.; Meng, H. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:24:57Z |
New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond
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Chung, Steve S.; Huang, D. C.; Tsai, Y. J.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:22:00Z |
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
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Lin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H. |
| 國立交通大學 |
2014-12-08T15:21:56Z |
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
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Chung, Steve S.; Hsieh, E. R.; Liu, P. W.; Chiang, W. T.; Tsai, S. H.; Tsai, T. L.; Huang, R. M.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:21:21Z |
A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
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Hsieh, E. R.; Chung, Steve S.; Liu, P. W.; Chiang, W. T.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H. |
| 國立交通大學 |
2014-12-08T15:10:03Z |
The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations
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Tsai, Y. J.; Chung, Steve S.; Liu, P. W.; Tsai, C. H.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
| 國立交通大學 |
2014-12-08T15:07:36Z |
Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices
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Chung, Steve S.; Tsai, Y. J.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W. |
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