臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
國立臺灣海洋大學	2009-07	Parallel Implementation of Convolution Encoder for Software Defined Radio on DSP Architecture	Jui-Chieh Lin;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen;Yu Hen Hu
國立臺灣海洋大學	2009-05	A 900 MHz to 5.2 GHz Dual-Loop Feedback Multi-band LNA	Jia-Wei Lin;Da-Tong Yen;Wei-Yi Hu;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen
國立臺灣海洋大學	2009-01	Design of a High-Speed Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications	Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen
國立臺灣海洋大學	2009	Low-Error Fixed-Width Modified Booth Multipliers	Chu Yu;Cheng-Hang Sung;Meng-Hsueh Chiang;Mao-Hsu Yen;Hwai-Tsu Hu
國立臺灣海洋大學	2008-10	SIMD-Wavefront Architecture for Computing the Dynamic Time Warping Algorithm	Mao-Hsu Yen;Yeong-Chang Maa;Chu Yu;Yi-Shan Chen;Yu-Hsiang Huang
國立臺灣海洋大學	2008	A Unified Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications	Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen
國立臺灣海洋大學	2008	A VLSI Architecture for Computing the Dynamic Space Warping Algorithm	Chun-Lung Wu;Chia-Yen Hsu;Yu-Hsiang Huang;Mao-Hsu Yen;Yeong-Chang Maa
國立臺灣海洋大學	2006	A Three-Stage Three-Sided Rearrangeable Switching Network for Interconnection Chip	Mao-Hsu Yen;Yeong-Chang Maa;Chin-Fa Hsieh;Shiuh-Chung Yi;
國立臺灣海洋大學	2001-11	A Three-stage One-sided Rearrangeable Polygonal Switching Network	Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan
國立臺灣海洋大學	2001	Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System	Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan
國立臺灣海洋大學	1999-10	Symmetric and programmable multi-chip module for rapid prototyping system	Mao-Hsu Yen; Sao-Jie Chen; Sanko H. Lan
國立臺灣科技大學	1999	Symmetric and programmable multi-chip module for rapid prototyping system	Mao-Hsu Yen;Sao-Jie Chen;Lan, S.H.
國立臺灣科技大學	1999	Polygonal routing network for FPGA/FPIC	Mao-Hsu Yen;Mon-Chau Shie;Lan, S.H.
國立臺灣海洋大學	1999	Polygonal Routing Network for FPGA/FPIC	Mao-Hsu Yen;Mon-Chau Shie;Sank0 H. Lan

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