English  |  正體中文  |  简体中文  |  Total items :0  
Visitors :  51652497    Online Users :  975
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"mao hsu yen"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 46-54 of 54  (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page

Institution Date Title Author
國立臺灣海洋大學 2008 A Unified Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen
國立臺灣海洋大學 2008 A VLSI Architecture for Computing the Dynamic Space Warping Algorithm Chun-Lung Wu;Chia-Yen Hsu;Yu-Hsiang Huang;Mao-Hsu Yen;Yeong-Chang Maa
國立臺灣海洋大學 2006 A Three-Stage Three-Sided Rearrangeable Switching Network for Interconnection Chip Mao-Hsu Yen;Yeong-Chang Maa;Chin-Fa Hsieh;Shiuh-Chung Yi;
國立臺灣海洋大學 2001-11 A Three-stage One-sided Rearrangeable Polygonal Switching Network Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan
國立臺灣海洋大學 2001 Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan
國立臺灣海洋大學 1999-10 Symmetric and programmable multi-chip module for rapid prototyping system Mao-Hsu Yen; Sao-Jie Chen; Sanko H. Lan
國立臺灣科技大學 1999 Symmetric and programmable multi-chip module for rapid prototyping system Mao-Hsu Yen;Sao-Jie Chen;Lan, S.H.
國立臺灣科技大學 1999 Polygonal routing network for FPGA/FPIC Mao-Hsu Yen;Mon-Chau Shie;Lan, S.H.
國立臺灣海洋大學 1999 Polygonal Routing Network for FPGA/FPIC Mao-Hsu Yen;Mon-Chau Shie;Sank0 H. Lan

Showing items 46-54 of 54  (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page