臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:42:24Z	An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensing	Yu, T.-H.;Yang, C.-H.;Markovi?, D.;?abri?, D.; Yu, T.-H.; Yang, C.-H.; Markovi?, D.; ?abri?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensing	Yu, T.-H.;Yang, C.-H.;Markovi?, D.;?abri?, D.; Yu, T.-H.; Yang, C.-H.; Markovi?, D.; ?abri?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A hardware-efficient VLSI architecture for hybrid sphere-MCMC detection	Yuan, F.-L.;Yang, C.-H.;Markovi?, D.; Yuan, F.-L.; Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A hardware-efficient VLSI architecture for hybrid sphere-MCMC detection	Yuan, F.-L.;Yang, C.-H.;Markovi?, D.; Yuan, F.-L.; Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A 75μW, 16-channel neural spike-sorting processor with unsupervised clustering	Karkare, V.;Gibson, S.;Yang, C.-H.;Chen, H.;Markovi?, D.; Karkare, V.; Gibson, S.; Yang, C.-H.; Chen, H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A 75μW, 16-channel neural spike-sorting processor with unsupervised clustering	Karkare, V.;Gibson, S.;Yang, C.-H.;Chen, H.;Markovi?, D.; Karkare, V.; Gibson, S.; Yang, C.-H.; Chen, H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios	Yu, T.-H.;Yang, C.-H.;?abri?, D.;Markovi?, D.; Yu, T.-H.; Yang, C.-H.; ?abri?, D.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:42:24Z	A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios	Yu, T.-H.;Yang, C.-H.;?abri?, D.;Markovi?, D.; Yu, T.-H.; Yang, C.-H.; ?abri?, D.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:14:45Z	A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs	Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T08:14:45Z	A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs	Yang, C.-H.;Yu, T.-H.;Markovi?, D.; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T07:36:39Z	A flexible DSP architecture for MIMO sphere decoding	Yang, C.-H.;Markovi?, D.; Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T07:36:39Z	A flexible DSP architecture for MIMO sphere decoding	Yang, C.-H.;Markovi?, D.; Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T07:03:34Z	A multi-core sphere decoder VLSI architecture for MIMO communications	Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG
臺大學術典藏	2018-09-10T07:03:34Z	A flexible VLSI architecture for extracting diversity and spatial multiplexing gains in MIMO channels	Yang, C.-H.; Markovi?, D.; CHIA-HSIANG YANG

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