臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2019-10-24T07:57:17Z	High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme	吳安宇;AN-YEU(ANDY) WU;Jyh-Ting (Justin) Lai;An-Yeu Wu;Meng-Da Yang; Meng-Da Yang; An-Yeu Wu; Jyh-Ting (Justin) Lai; AN-YEU(ANDY) WU; 吳安宇
臺大學術典藏	2019-10-24T07:57:17Z	High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme	吳安宇;AN-YEU(ANDY) WU;Jyh-Ting (Justin) Lai;An-Yeu Wu;Meng-Da Yang; Meng-Da Yang; An-Yeu Wu; Jyh-Ting (Justin) Lai; AN-YEU(ANDY) WU; 吳安宇
臺大學術典藏	2019-10-24T07:57:17Z	Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique	吳安宇;AN-YEU(ANDY) WU;Jyh-Ting Lai;An-Yeu Wu;Meng-Da Yang; Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai; AN-YEU(ANDY) WU; 吳安宇
臺大學術典藏	2019-10-24T07:57:17Z	Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique	吳安宇;AN-YEU(ANDY) WU;Jyh-Ting Lai;An-Yeu Wu;Meng-Da Yang; Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai; AN-YEU(ANDY) WU; 吳安宇

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