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Taiwan Academic Institutional Repository >
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"meng hsueh"
Showing items 1-15 of 15 (1 Page(s) Totally)
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| 國立成功大學 |
2022-09 |
Qualitative impact assessment of COVID-19 on the pedagogical, technological and social experiences of higher education students in Taiwan
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Morgan;Cyleen;Tsai;Meng-Che;Hsu;Ed, Chiehwen;Chow;Hsueh-Wen;Guo;How-Ran;Lee;Meng-Hsueh |
| 國立成功大學 |
2022-04 |
Simulation-Based Study of Low Minimum Operating Voltage SRAM With Inserted-Oxide FinFETs and Gate-All-Around Transistors
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Wu;Yi-Ting;Ding;Fei;Chiang;Meng-Hsueh;Chen;Jone, F.;Liu;King, Tsu-Jae |
| 國立成功大學 |
2022-01 |
Effects of smartphone numeric keypad designs on performance and satisfaction of elderly users
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Hsieh;Meng-Hsueh;Ho;Chun-Heng;Lee;I-Chen |
| 國立成功大學 |
2022 |
Validation of Diabetes Knowledge Questionnaire (DKQ) in the Taiwanese Population - Concurrent Validity with Diabetes-Specific Quality of Life Questionnaire Module
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Hsieh;Meng-Hsueh;Chen;Yu-Ching;Ho;Chun-Heng;Lin;Chung-Ying |
| 國立成功大學 |
2021-12 |
TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS
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Huang;Ya-Chi;Chiang;Meng-Hsueh;Wang;Shui-Jinn;Fossum;Jerry, G. |
| 國立成功大學 |
2021-11 |
Simulation-Based Study of High-Permittivity Inserted-Oxide FinFET With Low-Permittivity Inner Spacers
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Wu;Yi-Ting;Chiang;Meng-Hsueh;Chen;Jone, F.;Liu;King, Tsu-Jae |
| 國立成功大學 |
2021 |
Bilayer Modulation With Dual Vacancy Filaments by Intentionally Oxidized Titanium Oxide for Multilayer-hBN RRAM
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Chen;Po-An;Hsu;Wei-Chou;Chiang;Meng-Hsueh |
| 國立成功大學 |
2020-11-7 |
Design of metasurfaces to enable shear horizontal wave trapping
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Su;Yu-Chi;Chen;Tungyang;Ko;Li-Heng;Lu;Meng-Hsueh |
| 國立成功大學 |
2020 |
Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory
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Lee;Jia-Wei;Chiang;Meng-Hsueh |
| 國立成功大學 |
2019-04 |
Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology
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Wu;Yi-Ting;Ding;Fei;Connelly;Daniel;Chiang;Meng-Hsueh;Chen;Jone, F.;Liu;King, Tsu-Jae |
| 國立成功大學 |
2018-03 |
An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications
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Hsieh;Yu-Feng;Chen;Si-Hua;Chen;Nan-Yow;Lee;Wen-Jay;Tsai;Jyun-Hwei;Chen;Chun-Nan;Chiang;Meng-Hsueh;Lu;Darsen, Darsen D.;Kao;Kuo-Hsing |
| 國立成功大學 |
2017-10 |
Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology
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Wu;Yi-Ting;Ding;Fei;Connelly;Daniel;Zheng;Peng;Chiang;Meng-Hsueh;Chen;Jone, F.;Liu;King, Tsu-Jae |
| 國立成功大學 |
2017-07-21 |
All-zigzag graphene nanoribbons for planar interconnect application
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Chen;Po-An;Chiang;Meng-Hsueh;Hsu;Wei-Chou |
| 國立成功大學 |
2017-07 |
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors
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Chen;Chun-Yu;Lin;Jyi-Tsong;Chiang;Meng-Hsueh |
| 國立成功大學 |
2017-05 |
GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node
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Huang;Ya-Chi;Chiang;Meng-Hsueh;Wang;Shui-Jinn;Fossum;Jerry, G. |
Showing items 1-15 of 15 (1 Page(s) Totally)
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