English  |  正體中文  |  简体中文  |  Total items :2851816  
Visitors :  44928562    Online Users :  1479
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"ming dou ker"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 36-78 of 78  (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page

Institution Date Title Author
國立交通大學 2014-12-12T01:21:16Z 平面顯示器玻璃基板上具有位階轉換功能之類比輸出級電路設計 陳紹岐; Shao-Chi Chen; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:21:15Z 奈米互補式金氧半製程下之低漏電源箝制靜電放電防護電路 邱柏硯; Po-Yen Chiu; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:14:15Z 抑制熱載子劣化效應與閘極氧化層過壓之混合電壓輸入輸出緩衝器設計 蔡惠雯; Hui-Wen Tsai; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:14:14Z 薄膜電晶體的溫度係數模型以及玻璃基板上具溫度補償功能之參考電壓電路 陸亭州; Ting-Chou, Lu; 柯明道; 冉曉雯; Ming-Dou, Ker; Hsiao-Wen, Zan
國立交通大學 2014-12-12T01:14:02Z 積體電路之系統層級靜電放電暫態偵測電路設計 廖期聖; Chi-Sheng Liao; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:13:51Z 90奈米互補式金氧半製程下之多功能輸入/輸出元件庫設計 陳世範; Shih-Fan Chen; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:13:14Z 高壓製程之靜電放電防護元件設計 黃曄仁; Yeh-Jen Huang; 柯明道; Ming-Dou Ker
國立交通大學 2014-12-12T01:13:08Z 低溫複晶矽面板上之靜電放電耐受度研究 莊介堯; Jie-Yao Chuang; 柯明道; Ming-Dou Ker
中山醫學大學 2014-05-14 Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging Syu-Jyun Peng; Tomor Harnod; Jang-Zern Tsai; Ming-Dou Ker; Jun-Chern Chiou; Herming Chiueh; Chung-Yu Wu; Yue-Loong Hsin
義守大學 2014-02 Synthesis of uniform core–shell gelatin–alginate microparticles as intestine-released oral delivery drug carrier Keng-Shiang Huang;Chih-Hui Yang;Chao-Ping Kung;Alexandru Mihai Grumezescu;Ming-Dou Ker;Yung-Sheng Lin;Chih-Yu Wang
義守大學 2010-12 ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology Chang-Tzu Wang;Ming-Dou Ker
義守大學 2010-11 Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection Chih-Ting Yeh; Ming-Dou Ker
義守大學 2010-10 New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance Ming-Dou Ker;Cheng-Cheng Yen
義守大學 2010-09 Implementation of the cosine law for location awareness system Pei-Ju Lin;Yeng-Chang Huang;Yu-Jung Huang;Ming-Dou Ker
義守大學 2010-09 CORDIC implementation of RSSI localization method Yen-Chang Huang;Pei-Ju Lin;Yu-Jung Huang;Ming-Dou Ker
義守大學 2010-08 Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications Tzu-Ming Wang;Ming-Dou Ker
義守大學 2010-07 High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process Ming-Dou Ker;Chun-Yu Lin
義守大學 2010-06 Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology Shih-Hung Chen;Ming-Dou Ker
義守大學 2010-06 Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme Chun-Yu Lin;Ming-Dou Ker;Yuan-Wen Hsiao
義守大學 2010-06 Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits Chih-Ting Yeh;Ming-Dou Ker;Yung-Chih Liang
義守大學 2010-06 Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology Chang-Tzu Wang;Ming-Dou Ker
義守大學 2010-05 Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process Wen-Yi Chen;Ming-Dou Ker
義守大學 2010-02 New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS Wen-Yi Chen;Ming-Dou Ker
義守大學 2010-01 Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation Hui-Wen Tsai;Ming-Dou Ker
義守大學 2009-09 New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process Ming-Dou Ker ; Wen-Yi Chen ; Wuu-Trong Shieh ; I-Ju Wei
義守大學 2009-09 Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application Tzu-Ming Wang;Ming-Dou Ker;Sao-Chi Chen
義守大學 2009-08 Transient-Induced Latchup in CMOS Integrated Circuits 柯明道;Ming-Dou Ker; Sheng-Fu Hsu
義守大學 2009-08 Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs Ming-Dou Ker;Cheng-Cheng Yen
義守大學 2009-08 Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology Jung-Sheng Chen;Ming-Dou Ker
義守大學 2009-07 Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection Shih-Hung Chen;Ming-Dou Ker
義守大學 2009-06 Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process Yuan-Wen Hsiao;Ming-Dou Ker
義守大學 2009-06 Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test Cheng-Cheng Yen;Ming-Dou Ker;Tung-Yang Chen
義守大學 2009-06 The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps Cheng-Cheng Yen;Ming-Dou Ker
義守大學 2009-05 Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs Shih-Hung Chen;Ming-Dou Ker
義守大學 2009-05 A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process Yuan-Wen Hsiao;Ming-Dou Ker
義守大學 2009-05 Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology Tzu-Ming Wang; Ming-Dou Ker; Hung-Tai Liao
義守大學 2009-04 High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection Wen-Yi Chen;Ming-Dou Ker
義守大學 2009-03 Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits Ming-Dou KER;Yuan-Wen HSIAO
義守大學 2009-03 Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes Ming-Dou Ker;Chang-Tzu Wang
義守大學 2009-03 Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology Chang-Tzu Wang;Ming-Dou Ker
義守大學 2008-12 Investigation on Board-Level CDM ESD Issue in IC Products Ming-Dou Ker;Yuan-Wen Hsiao
義守大學 2008-11 Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology Ming-Dou Ker;Tai-Hsiang Lai
義守大學 2008-11 Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test Ming-Dou Ker;Cheng-Cheng Yen

Showing items 36-78 of 78  (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page