臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

	English \| 正體中文 \| 简体中文 \| 總筆數 :2851812
	造訪人次 : 44825878 線上人數 : 1458 教育部委託研究計畫計畫執行:國立臺灣大學圖書館

搜尋範圍

進階搜尋

登入

管理

臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

關於TAIR
	計畫說明

瀏覽
	典藏機構
	作者
	題名
	日期
	統計圖表
	機構即時統計
	學術趨勢

消息
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

著作權
	出版社及期刊政策查詢
	TAIR著作權會議記錄

相關連結
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"ming dou ker"的相關文件

回到依作者瀏覽
依題名排序	依日期排序

顯示項目 61-78 / 78 (共2頁)
<< < 1 2
每頁顯示[10|25|50]項目

機構	日期	題名	作者
義守大學	2009-09	Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application	Tzu-Ming Wang;Ming-Dou Ker;Sao-Chi Chen
義守大學	2009-08	Transient-Induced Latchup in CMOS Integrated Circuits	柯明道;Ming-Dou Ker; Sheng-Fu Hsu
義守大學	2009-08	Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs	Ming-Dou Ker;Cheng-Cheng Yen
義守大學	2009-08	Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology	Jung-Sheng Chen;Ming-Dou Ker
義守大學	2009-07	Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection	Shih-Hung Chen;Ming-Dou Ker
義守大學	2009-06	Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process	Yuan-Wen Hsiao;Ming-Dou Ker
義守大學	2009-06	Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test	Cheng-Cheng Yen;Ming-Dou Ker;Tung-Yang Chen
義守大學	2009-06	The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps	Cheng-Cheng Yen;Ming-Dou Ker
義守大學	2009-05	Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs	Shih-Hung Chen;Ming-Dou Ker
義守大學	2009-05	A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process	Yuan-Wen Hsiao;Ming-Dou Ker
義守大學	2009-05	Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology	Tzu-Ming Wang; Ming-Dou Ker; Hung-Tai Liao
義守大學	2009-04	High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection	Wen-Yi Chen;Ming-Dou Ker
義守大學	2009-03	Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits	Ming-Dou KER;Yuan-Wen HSIAO
義守大學	2009-03	Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes	Ming-Dou Ker;Chang-Tzu Wang
義守大學	2009-03	Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology	Chang-Tzu Wang;Ming-Dou Ker
義守大學	2008-12	Investigation on Board-Level CDM ESD Issue in IC Products	Ming-Dou Ker;Yuan-Wen Hsiao
義守大學	2008-11	Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology	Ming-Dou Ker;Tai-Hsiang Lai
義守大學	2008-11	Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test	Ming-Dou Ker;Cheng-Cheng Yen

顯示項目 61-78 / 78 (共2頁)
<< < 1 2
每頁顯示[10|25|50]項目