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Showing items 1-12 of 12 (1 Page(s) Totally)
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| 亞洲大學 |
2015-04 |
Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage
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Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
2015-04 |
Optimization of Holding Voltage for 5V multi-finger NMOS using Voltage stepping simulation
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Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
2015-03 |
High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance
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楊紹明;Yang, Shao-Ming;*; Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS
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楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
High Voltage NLDMOS with Multiple-RESURF Structure to Achieve Improved On-resistance
|
楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;陳柏安;Chen, PA |
| 亞洲大學 |
2015-03 |
A HSPICE Macro Model for the ESD Behavior of Gate Grounded NMOS and Gate coupled NMOS
|
楊紹明;Yang, Shao-Ming;Hema, EP;Hema, EP;許健;Sheu, Gene;Mri, Aryadeep;Mrinal, Aryadeep;Md.Amanulla;Md.Amanullah;陳柏安;Chen, PA |
| 亞洲大學 |
2014-06-12 |
Development of SiC Schottky Diode with Linear P-top rings and Optimization of NLD 40V for Higher breakdown voltage and lower On-Resistance
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Mrinal, Aryadeep |
| 亞洲大學 |
2014-01 |
Optimization of SiC Schottky Diode using Linear P-top for Edge
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek N, Man;Vivek N, Manjunatha M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
201310 |
Optimization of SiC Schottky Diode using Linear P for Edge Termination
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Mri, Aryadeep;Mrinal, Aryadeep;Kumar, Vijay;Vivek, N;Vivek, N;Manjunatha, M;Manjunatha, M;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
201310 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
| 亞洲大學 |
201310 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
2013-10 |
Effect of Trench Depth and Trench Angle in a High Voltage Polyflanked-Super junction MOSFET
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Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Nidhi, Karuna;Nidhi, Karuna;Agarw, Neelam;Agarwal, Neelam;Kumar, Ankit;Kumar, Ankit;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Mri, Aryadeep;Mrinal, Aryadeep |
Showing items 1-12 of 12 (1 Page(s) Totally)
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