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| 國立交通大學 |
2020-05-05T00:02:22Z |
Improving breakdown voltage for 120 V level up shifter by using vertical and lateral assisted depletion layers in 0.35 mu m CMOS technology
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Chen, Po-An; Lin, Kuang-Lun; Lin, Horng-Chih; Ningaraju, Vivek |
| 國立交通大學 |
2019-04-02T06:04:21Z |
A New High Voltage IC with Robust Isolation Design
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Ningaraju, Vivek; Lin, Horng-Chih; Chen, Po-An; Wen, Jiin-Shiarng |
| 亞洲大學 |
2015-04 |
Improvement of On-Resistance Degradation Induced by Hot Carrier
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Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
2015-04 |
Simulation of P-type Doping Profile Prediction Using
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Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
2015-04 |
Simulation of P-type Doping Profile Prediction Using Different Ion Implantation and Diffusion Model
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Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
2015-04 |
Improvement of On-Resistance Degradation Induced by Hot Carrier Injection in SOI-LDMOS
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Ningar, Vivek;Ningaraju, Vivek |
| 亞洲大學 |
201310 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek |
Showing items 1-7 of 7 (1 Page(s) Totally)
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