English  |  正體中文  |  简体中文  |  2817030  
???header.visitor??? :  27627457    ???header.onlineuser??? :  613
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"p f lin"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 1-4 of 4  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
臺大學術典藏 2018-09-10T07:41:35Z A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T04:15:05Z A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T03:50:14Z A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T03:50:14Z A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell P. F. Lin; J. B. Kuo; P. F. Lin; J. B. Kuo; JAMES-B KUO

Showing items 1-4 of 4  (1 Page(s) Totally)
1 
View [10|25|50] records per page