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| 臺大學術典藏 |
2020-04-16T02:35:16Z |
MARS: a RISC-based architecture for Lisp
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Lee, H.-C.;Lai, F.;Tsai, J.-Y.;Parng, T.-M.; Lee, H.-C.; Lai, F.; Tsai, J.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
A memory management unit and cache controller for the MARS system
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Lai, F.;Wu, C.-Y.;Parng, T.-M.; Lai, F.; Wu, C.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI architecture design and implementation for TWOFISH block cipher
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Lai, Y.-K.; Chen, L.-G.; Lai, J.-Y.; Parng, T.-M.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:43:47Z |
ASG: Automatic schematic generator
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Jehng, Y.-S.; Chen, L.-G.; Parng, T.-M.; LIANG-GEE CHEN |
| 國立臺灣大學 |
1994-02 |
Mapping iterative networks to parallel lookahead circuits
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Shyur, J.-C.; Parng, T.-M. |
| 臺大學術典藏 |
1993 |
Intelligent stock trading system with price trend prediction and reversal recognition using dual-module neural networks
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Jang, G.-S.;Lai, F.;Jiang, B.-W.;Parng, T.-M.;Chien, L.-H.; Jang, G.-S.; Lai, F.; Jiang, B.-W.; Parng, T.-M.; Chien, L.-H.; FEI-PEI LAI |
| 淡江大學 |
1992-09-01 |
MARS: a RISC based multiple function units Lisp machine
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李鴻璋; Lee, H. C.; Lai, F.; Parng, T. M. |
| 淡江大學 |
1989-09 |
List processing unit : architecture & implementation
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李鴻璋; Lee, H. C. ; Lai, F. ; Parng, T. M. ; Tsai, J. Y. |
| 淡江大學 |
1989-05 |
Multiprocessor architecture reconciling symbolic with numerical processing
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Jang, G. S. ; Lai, F. ; 李鴻璋; Lee, H. C. ; Maa, Y. C. ; Parng, T. M. ; Tsai, J. Y. |
| 國立臺灣大學 |
1988-10 |
A rule-based compactor for VLSI/CAD mask layout
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Hsiao, Pei-Yung; Chen, Yung Syau; Feng, Wu-Shiung; Parng, T.M.; Hsu, C.C. |
Showing items 1-10 of 10 (1 Page(s) Totally)
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