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| 國立臺灣大學 |
1991 |
MARS:Zero-Delay Branch List Access Architecture
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賴飛羆; Horng, Cheun-Jing; Parng, Tai-Ming; Lai, Fei-Pei; Horng, Cheun-Jing; Parng, Tai-Ming |
| 臺大學術典藏 |
1991 |
MARS:Zero-Delay Branch List Access Architecture
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Parng, Tai-Ming; Lai, Fei-Pei; Horng, Cheun-Jing; 賴飛羆; Horng, Cheun-Jing; Parng, Tai-Ming; Lai, Fei-Pei; Horng, Cheun-Jing |
| 國立臺灣大學 |
1990-11 |
A memory management unit and cache controller for the MARS system
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Lai, Feipei; Wu, Chyuan-Yow; Parng, Tai-Ming |
| 國立臺灣大學 |
1990-04 |
MARS performance evaluation with different interconnection networks
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Lai, Feipei; Tzeng, Lea-Ming; Chang, Thom-Ling; Parng, Tai-Ming |
| 淡江大學 |
1990-03 |
MARS: aRISC-based architecture for Lisp
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Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-yuan; Parng, Tai-ming |
| 國立臺灣大學 |
1990 |
智慧型超大型積體電路設計自動化系統;自動化發展架構之建立,電路圖自動產生器
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龐台銘; Parng, Tai-Ming |
| 國立臺灣大學 |
1990 |
MARS: a RISC-based architecture for Lisp
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Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming |
| 國立臺灣大學 |
1989-10 |
MARS-a RISC-based architecture for LISP
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Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming; Li, Yu-Gang |
| 國立臺灣大學 |
1989-05 |
MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
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Jang, Gia-Shuh; Lai, Feipei; Lee, Hung-Chang; Maa, Yeong-Chang; Parng, Tai-Ming; Tsai, Jenn-Yuan |
| 國立臺灣大學 |
1989 |
智慧型超大型積體電路設計自動化系統;自動化發展架構之建立. 階層式設計資料庫之行為環境
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龐台銘; Parng, Tai-Ming |
| 國立臺灣大學 |
1988-06 |
A database management system for a VLSI design system
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Chen, Gwo-Dong; Parng, Tai-Ming |
| 國立臺灣大學 |
1988 |
超大型積體電路之元件模擬
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龐台銘; 馮武雄; Parng, Tai-Ming; 馮武雄 |
| 國立臺灣大學 |
1988 |
整合式超大型積體電路設計系統:設計驗證系統
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龐台銘; Parng, Tai-Ming |
| 國立臺灣大學 |
1988 |
積體式CAD/VLSI模擬系統
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龐台銘; 馮武雄; Parng, Tai-Ming; 馮武雄 |
| 國立臺灣大學 |
1988 |
A Rule-Based Compactor for VLSI/CAD Mask Layout
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Hsiao, P. Y.; Syau, C. Y.; 馮武雄; 龐台銘; Hsu, C. C.; Hsiao, P. Y.; Syau, C. Y.; Feng, Wu-Shiung; Parng, Tai-Ming; Hsu, C. C. |
| 國立臺灣大學 |
1987 |
整合式超大型積體電路設計系統
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于惠中; 龐台銘; 林呈祥; Yu, Hui-Jung; Parng, Tai-Ming; Lin, Chen-Shang |
| 國立臺灣大學 |
1986-08 |
Schematic Layout Editor
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Wang, C. I.; 馮武雄; 龐台銘; Wang, C. I.; Feng, Wu-Shiung; Parng, Tai-Ming |
| 國立臺灣大學 |
1986 |
計算機網路作業系統之研製
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龐台銘; Parng, Tai-Ming |
| 國立臺灣大學 |
1986 |
整合式超大型積體電路設計系統:設計輸入及佈局系統
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龐台銘; Parng, Tai-Ming |
| 國立臺灣大學 |
1986 |
Data Path Modeling and Synthesizing for Digital Systems
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Sun, L. F.; 龐台銘; 馮武雄; Sun, L. F.; Parng, Tai-Ming; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986 |
Integrated Entry and Verification System
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Yuan, Y. C.; 馮武雄; 龐台銘; Yuan, Y. C.; Feng, Wu-Shiung; Parng, Tai-Ming |
| 國立臺灣大學 |
1984 |
超大型積體電路電腦網路輔助設計系統-子計畫七
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龐台銘; 闕志達; Parng, Tai-Ming; Chiueh, Tzi-Dar |
| 國立臺灣大學 |
1977 |
多晶片模組設計自動化與測試系統子計畫二: 多晶片模組佈局工具之研製
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闕志達; 龐台銘; Chiueh, Tzi-Dar; Parng, Tai-Ming |
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