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Showing items 1-9 of 9 (1 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:04:42Z |
Active device under bond pad to save I/O layout for high-pin-count SOC
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:42:20Z |
Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
|
Ker, MD; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:41:45Z |
Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
|
Ker, MD; Hsu, HC; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:40:18Z |
ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
|
Ker, MD; Hsu, HC; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:26:50Z |
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
|
Ker, MD; Jiang, HC; Peng, JJ; Shieh, TL |
| 國立交通大學 |
2014-12-08T15:26:38Z |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
|
Peng, JJ; Ker, MD; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:23Z |
Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits
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Ker, MD; Hsu, HC; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:26:13Z |
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
|
Ker, MD; Peng, JJ; Jiang, HC |
Showing items 1-9 of 9 (1 Page(s) Totally)
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