臺大學術典藏 |
2018-09-10T08:46:02Z |
Passive equalizer design for through silicon vias with perfect compensation
|
R.-B. Sun; C.-Y. Wen; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T08:46:01Z |
A new isolation structure of pogo pins for crosstalk reduction in a test socket
|
R.-B. Sun; C.-Y. Wen; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T08:17:53Z |
Compromise impedance match design for pogo pins with different single-ended and differential signal-ground patterns
|
R.-B. Sun;R.-B. Wu;S.-W. Hsiao;D. De Zutter; R.-B. Sun; R.-B. Wu; S.-W. Hsiao; D. De Zutter; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T08:17:53Z |
Compromise impedance match design for pogo pins with different single-ended and differential signal-ground patterns
|
R.-B. Sun;R.-B. Wu;S.-W. Hsiao;D. De Zutter; R.-B. Sun; R.-B. Wu; S.-W. Hsiao; D. De Zutter; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T08:17:53Z |
RC passive equalizer for through silicon via
|
R.-B. Sun;C.-Y. Wen;R.-B. Wu; R.-B. Sun; C.-Y. Wen; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T08:17:53Z |
RC passive equalizer for through silicon via
|
R.-B. Sun;C.-Y. Wen;R.-B. Wu; R.-B. Sun; C.-Y. Wen; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T07:41:22Z |
A new isolation structure for crosstalk reduction for pogo pins in a test socket
|
R.-B. Sun;C.-Y. Wen;Y.-C. Chang;R.-B. Wu; R.-B. Sun; C.-Y. Wen; Y.-C. Chang; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T07:41:22Z |
A new isolation structure for crosstalk reduction for pogo pins in a test socket
|
R.-B. Sun;C.-Y. Wen;Y.-C. Chang;R.-B. Wu; R.-B. Sun; C.-Y. Wen; Y.-C. Chang; R.-B. Wu; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T07:41:21Z |
Compromised impedance match design for signal integrity of pogo pins structures with different signal-ground patterns
|
R.-B. Sun;R.-B. Wu;S.-W. Haiso; R.-B. Sun; R.-B. Wu; S.-W. Haiso; RUEY-BEEI WU |
臺大學術典藏 |
2018-09-10T07:41:21Z |
Compromised impedance match design for signal integrity of pogo pins structures with different signal-ground patterns
|
R.-B. Sun;R.-B. Wu;S.-W. Haiso; R.-B. Sun; R.-B. Wu; S.-W. Haiso; RUEY-BEEI WU |