| 淡江大學 |
2009-11-23 |
A New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
|
Chen, Tsung-tang; Li, Wei-lin; Wu, Po-han; Rau, Jiann-chyi |
| 淡江大學 |
2009-11 |
Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment
|
Wu, Po-han; Rau, Jiann-chyi |
| 淡江大學 |
2009-05-24 |
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression
|
Li, Wei-Lin; Wu, Po-Han; Rau, Jiann-Chyi |
| 淡江大學 |
2009-01 |
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
|
Rau, Jiann-chyi; Wu, Po-han; Liu, Chia-jung; Lin, Yi-chen |
| 淡江大學 |
2008-11 |
The Efficient TAM Design for Core-Based SOCs Testing
|
Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu |
| 淡江大學 |
2008-08-31 |
The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design
|
Liu, Chia-Jung; Lin, Yi-Chen; Rau, Jiann-Chyi |
| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-06 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu |
| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
|
Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006-05 |
A broadcast-based test scheme for reducing test size and application time
|
Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun |
| 淡江大學 |
2005-05-23 |
Reconfigurable multiple scan-chains for reducing test application time of SOCs
|
Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
| 淡江大學 |
2004-11 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
Rau, Jiann-Chyi; Lin, Ching-Hsiu; Chang, Jun-Yi |
| 淡江大學 |
2004-07 |
以Layout為基礎的高效率多重掃描鍊最佳化
|
饒建奇; Rau, Jiann-chyi |
| 淡江大學 |
2004-05 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004-05 |
Built-In Reseeding With Modifying Technique For Bist
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2004-05 |
The optimal testrail architecture for core-based soc testing
|
Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung |
| 淡江大學 |
2004 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2003-08 |
A Datapath-Based Debugging Mechanism for RTL Description
|
Rau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao |
| 淡江大學 |
2003-08 |
Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
|
Rau, Jiann-Chyi; Kuo, Kuo-Chun; Yang, Ta-Wei |
| 淡江大學 |
2003-08 |
A Core-Based Test Methodology for Fast Multipliers
|
Rau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu |
| 淡江大學 |
2003 |
An Efficient Test Strategy for Fast Multiplier Cores
|
Rau, Jiann-chyi; Lin, Chia-hung; Lin, Ching-hsiu |
