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"rau jiann chyi"的相关文件
显示项目 21-30 / 44 (共5页)
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| 淡江大學 |
2008-08-31 |
The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design
|
Liu, Chia-Jung; Lin, Yi-Chen; Rau, Jiann-Chyi |
| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-06 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu |
| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
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Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006-05 |
A broadcast-based test scheme for reducing test size and application time
|
Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun |
| 淡江大學 |
2005-05-23 |
Reconfigurable multiple scan-chains for reducing test application time of SOCs
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Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
| 淡江大學 |
2004-11 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
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Rau, Jiann-Chyi; Lin, Ching-Hsiu; Chang, Jun-Yi |
| 淡江大學 |
2004-07 |
以Layout為基礎的高效率多重掃描鍊最佳化
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饒建奇; Rau, Jiann-chyi |
显示项目 21-30 / 44 (共5页)
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