| 淡江大學 |
2021-11-16 |
A Scan-Based Lower-Power Testing Architecture for Modern Circuits
|
Rau, Jiann-Chyi;Wang, Jia-Xiang |
| 淡江大學 |
2018-04-13 |
Low-Capture-Power X-filling Method Base On Architecture Using Selection Expansion
|
Chung, Yu-Ting;Rau, Jiann-Chyi |
| 淡江大學 |
2013-06 |
Compact Test Pattern Selection for Small Delay Defect
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Chia-Yuan Chang; Kuan-Yu Liao; Sheng-Chang Hsu; Li, J.C.; Rau, Jiann-Chyi |
| 淡江大學 |
2012-11 |
Optimal Unknown Bit Filtering for Test Response Masking
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Weng, Ding-ke; Rau, Jiann-Chyi; Lin , Cheng-han |
| 淡江大學 |
2012-11 |
An Efficient Test Data Compression Scheme Using Selection Expansion
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Rau, Jiann-chyi |
| 淡江大學 |
2012-11 |
Multimode ATPG for DVFS Designs
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Bai, B.; Lin, J.; Rau, Jiann-chyi |
| 淡江大學 |
2012-10-18 |
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
|
Shih, Chi-Jih; Hsu, Chih-Yao; Kuo, Chun-Yi; Li, James; Rau, Jiann-Chyi; Krishnendu Chakrabarty |
| 淡江大學 |
2012-06 |
Test Slice Difference Technique for Low-Transition Test Data Compression
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Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin |
| 淡江大學 |
2011-06 |
Power-aware compression scheme for multiple scan-chain
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Rau, Jiann-Chyi; Wu, Po-Han |
| 淡江大學 |
2011-03 |
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
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Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han |
| 淡江大學 |
2011-01 |
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
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Rau, Jiann-Chyi; Wu, Po-Han |
| 淡江大學 |
2010-10-31 |
The AB-Filling Methodology for Power-aware At-Speed Scan Testing
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Chen, Tsung-tang; Wu, Po-han; Chen, Kung-han; Rau, Jiann-chyi; Tzeng, Shih-ming |
| 淡江大學 |
2010-09 |
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
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Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun |
| 淡江大學 |
2010-05-30 |
Multi-Chains Encoding Scheme in Low-Cost ATE
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饒建奇; Rau, Jiann-Chyi; Chen, Gong-Han; Wu, Po-Han |
| 淡江大學 |
2010-05-30 |
Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
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饒建奇; Rau, Jiann-Chyi; Lin, Chu-Chuan; Wu, Po-Han; Chen, Gong-Han |
| 淡江大學 |
2009-11-23 |
A New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
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Chen, Tsung-tang; Li, Wei-lin; Wu, Po-han; Rau, Jiann-chyi |
| 淡江大學 |
2009-11 |
Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment
|
Wu, Po-han; Rau, Jiann-chyi |
| 淡江大學 |
2009-05-24 |
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression
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Li, Wei-Lin; Wu, Po-Han; Rau, Jiann-Chyi |
| 淡江大學 |
2009-01 |
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
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Rau, Jiann-chyi; Wu, Po-han; Liu, Chia-jung; Lin, Yi-chen |
| 淡江大學 |
2008-11 |
The Efficient TAM Design for Core-Based SOCs Testing
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Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu |
| 淡江大學 |
2008-08-31 |
The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design
|
Liu, Chia-Jung; Lin, Yi-Chen; Rau, Jiann-Chyi |
| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-06 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu |
| 淡江大學 |
2008-06 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing |
| 淡江大學 |
2006-12-04 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
|
Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han |
| 淡江大學 |
2006-05 |
A broadcast-based test scheme for reducing test size and application time
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Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun |
| 淡江大學 |
2005-05-23 |
Reconfigurable multiple scan-chains for reducing test application time of SOCs
|
Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing |
| 淡江大學 |
2005-05-23 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han |
| 淡江大學 |
2004-11 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
Rau, Jiann-Chyi; Lin, Ching-Hsiu; Chang, Jun-Yi |
| 淡江大學 |
2004-07 |
以Layout為基礎的高效率多重掃描鍊最佳化
|
饒建奇; Rau, Jiann-chyi |
| 淡江大學 |
2004-05 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004-05 |
Built-In Reseeding With Modifying Technique For Bist
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2004-05 |
The optimal testrail architecture for core-based soc testing
|
Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung |
| 淡江大學 |
2004 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
|
Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
|
Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2003-08 |
A Datapath-Based Debugging Mechanism for RTL Description
|
Rau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao |
| 淡江大學 |
2003-08 |
Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
|
Rau, Jiann-Chyi; Kuo, Kuo-Chun; Yang, Ta-Wei |
| 淡江大學 |
2003-08 |
A Core-Based Test Methodology for Fast Multipliers
|
Rau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu |
| 淡江大學 |
2003 |
An Efficient Test Strategy for Fast Multiplier Cores
|
Rau, Jiann-chyi; Lin, Chia-hung; Lin, Ching-hsiu |
| 淡江大學 |
2002-08 |
A Novel BIST Response Analyzer Based on TLS
|
Rau, Jiann-Chyi; Jone, Wen-Ben |
| 淡江大學 |
2001-08 |
The methods to construct imaging circuit for efficient VLSI circuit verification
|
饒建奇; Rau, Jiann-chyi; Chen, Y. M.; Chang, S. C. |
| 淡江大學 |
2001-01 |
A timing driven pseudo exhaustive testing for VLSI circuits
|
Chang, Shih-chieh; 饒建奇; Rau, Jiann-chyi |
| 淡江大學 |
2000-10 |
Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
|
Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L. |
