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"rau jiann chyi"
Showing items 31-40 of 44 (5 Page(s) Totally)
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| 淡江大學 |
2004-05 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004-05 |
Built-In Reseeding With Modifying Technique For Bist
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Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2004-05 |
The optimal testrail architecture for core-based soc testing
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Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung |
| 淡江大學 |
2004 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
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Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi |
| 淡江大學 |
2004 |
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
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Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu |
| 淡江大學 |
2003-08 |
A Datapath-Based Debugging Mechanism for RTL Description
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Rau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao |
| 淡江大學 |
2003-08 |
Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
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Rau, Jiann-Chyi; Kuo, Kuo-Chun; Yang, Ta-Wei |
| 淡江大學 |
2003-08 |
A Core-Based Test Methodology for Fast Multipliers
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Rau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu |
| 淡江大學 |
2003 |
An Efficient Test Strategy for Fast Multiplier Cores
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Rau, Jiann-chyi; Lin, Chia-hung; Lin, Ching-hsiu |
Showing items 31-40 of 44 (5 Page(s) Totally)
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