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Institution Date Title Author
國立臺灣科技大學 2011-06 The 10 GHz wide tuning and low phase-noise PLL chip design Jhin-Fang Huang;Che-Chi Mao;Ron-Yi Liu
國立臺灣科技大學 2011-04 Chip Design of an UWB, High Gain and Low Noise Amplifier for Wireless Applications Jhin-Fang Huang;Ming-Chun Hsu;Jiun-Yu Wen;Ron-Yi Liu
國立臺灣科技大學 2011-04 The RF receiver front-end chip design with the transformer balun for DSRC applications Jhin-Fang Huang;Yong-Jhen Jiangn;Ron-Yi Liu
國立臺灣科技大學 2010-10 Chip design of an 8 MHz CMOS switched-capacitor low-pass filter for signal receiver applications Jhin-Fang Huang;Jiun-Yu Wen;Yan-Cheng Lai;Ron-Yi Liu
國立臺灣科技大學 2009-11 Chip design of phase-locked loop for ISM band applications Jhin-Fang Huang;Po-Ching Li;Jiun-Yu Wen;Ron-Yi Liu
元智大學 2003-06 A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a 吳紹懋; Ron-Yi Liu; Wei-Liang Chen
元智大學 2002-08 A 5.8Ghz CMOS RF Image-Rejection Receiver Front-end using 90-degree Delayed-Lock Loop 吳紹懋; Ron-Yi Liu; Sin-Yu Chen

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