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Institution Date Title Author
國立臺灣科技大學 2018 A design for testability of open defects at interconnects in 3D stacked ICs Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z.
國立臺灣科技大學 2016 A built-in electrical test circuit for detecting open leads in assembled PCB circuits Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z.
國立臺灣科技大學 2016 A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z.
國立臺灣科技大學 2013 Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z.
國立臺灣科技大學 2013 DFT for supply current testing to detect open defects at interconnects in 3D ICs Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z.

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