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Institution Date Title Author
亞洲大學 1995-02 On the Construction of a Prolog-Based Verifier for Systolic Designs Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
亞洲大學 1992 Program Generation and Controls in a Specification Processing Environment, Timothy K. Shih;Ruth Davis
亞洲大學 1992 A Specification Processing Environment for Making Well Engineered Logic Programs Timothy K. Shih; Ruth Davis; Rob Langsner
亞洲大學 1992 Intelligence Backtracking and Controls Based on a Deduction Status Representation in Logic Programming Timothy K. Shih;Ruth Davis
亞洲大學 1992 Using Prolog as a Tool for Systolic Array Designs Fuyau Lin; Timothy K. Shih; Nam Lin; Ruth Davis
亞洲大學 1992 An Automatic Design Specification and Verification Tool for Systolic Architecture Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
亞洲大學 1991 Automatic Formal Verification of Systolic Array Designs Nam Ling; Fuyau Lin; Timothy K. Shih;Ruth Davis

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