| 臺大學術典藏 |
2018-09-10T04:12:45Z |
An H-V Alternating Router
|
Tsai, C.-C.; Chen, S.-J.; Feng, W.-S.; Tsai, C.-C.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T04:12:44Z |
VERTAF: An object-oriented application framework for embedded real-time systems
|
Hsiung, P.-A.; Lee, T.-Y.; See, W.-B.; Fu, J.-M.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T04:12:44Z |
Printed circuit board routing and package layout codesign
|
Chen, S.-S.; Tseng, W.-D.; Yan, J.-T.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:47:51Z |
A three-stage one-sided rearrangeable polygonal switching network
|
Lan, S.H.; SAO-JIE CHEN; Yen, M.-H.; Chen, S.-J. |
| 臺大學術典藏 |
2018-09-10T03:47:51Z |
New iterative construction approach to routing with compacted area
|
Tsai, C.-C.; Chen, S.-J.; Hsiao, P.-Y.; Feng, W.-S.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:47:51Z |
Routing Area Compaction Based On Iterative Construction
|
Tsai, C.-C.; Chen, S.-J.; Hsiao, P.-Y.; Feng, W.-S.; SAO-JIE CHEN; Tsai, C.-C.;Chen, S.-J.;Hsiao, P.-Y.;Feng, W.-S. |
| 臺大學術典藏 |
2018-09-10T03:47:50Z |
Hardware-software multi-level partitioning for distributed embedded multiprocessor systems
|
Lee, T.-Y.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:47:50Z |
Formal verification of embedded real-time software in component-based application frameworks
|
Hsiung, P.-A.; See, W.-B.; Lee, T.-Y.; Fu, J.-M.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:47:50Z |
DESC: A hardware-software codesign methodology for distributed embedded systems
|
Lee, T.-Y.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:47:50Z |
A wire segment reassignment algorithm for minimizing crosstalk for strait-type river routing
|
Cherng, J.-S.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:32Z |
GM_Plan: A Gate Matrix Layout Algorithm Based on Artificial Intelligence Planning Techniques
|
Hu, Y.H.;Chen, S.-J.; Hu, Y.H.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:32Z |
Generalized terminal connectivity problem for multilayer layout scheme
|
Tsai, C.-C.;Chen, S.-J.;Feng, W.-S.; Tsai, C.-C.; Chen, S.-J.; Feng, W.-S.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Hard ware-software timing co-verification of distributed embedded systems
|
Jih-Ming, F.U.; Lee Trong-Yen; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Automatic router for the pin grid array package
|
Chen, S.-S.; Chen, J.-J.; Tsai, C.-C.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T03:29:31Z |
Tutorial on VLSI partitioning
|
Chen, S.-J.; Cheng, C.-K.; SAO-JIE CHEN |
| 國立臺灣海洋大學 |
2012-01 |
Design of a Low-Power OFDM Baseband Receiver for Wireless Communications
|
Chu YU; Chien-Hung Kuo; Chen-Hen Sung; Mao-Hsu Yen; Sao-Jie Chen |
| 國立臺灣海洋大學 |
2012 |
Design and Implementation of a Low-Power OFDM Receiver for Wireless Communications
|
Chu Yu;Chen-Hen Sung;Chien-Hung Kuo;Mao-Hsu Yen;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2012 |
An adaptive reasoning and learning framework for cognitive radios
|
Chih-Sheng Lin;Ken-Shin Huang;Jih-Sheng Shen;Shen-Yang Pan;Shih-Shen Lu;Wei-Wen Lin;Pao-Ann Hsiung;Mao-Hsu Yen;Chu Yu;Sao-Jie Chen;W. C.-C. Chu |
| 臺大學術典藏 |
2012 |
Reconfigurable networks-on-chip
|
Chen, S.-J.; Lan, Y.-C.; Tsai, W.-C.; Hu, Y.-H.; SAO-JIE CHEN |
| 國立臺灣海洋大學 |
2011-02 |
A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications
|
Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2011-01 |
A Novel Low-Power 64-Point Pipelined FFT/IFFT Processor for OFDM Applications
|
Chu Yu;Yi-Ting Liao;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2011 |
A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications
|
Chu Yu ; Mao-Hsu Yen ; Pao-Ann Hsiung ; Sao-Jie Chen |
| 國立臺灣海洋大學 |
2010-07 |
ARAL-CR: An Adaptive Reasoning And Learning Cognitive Radio Platform
|
Sao-Jie Chen;Pao-Ann Hsiung;Chu Yu;Mao-Hsu Yen;Sezer S.;Schulte M.;Yu-Hen Hu |
| 國立臺灣海洋大學 |
2010-06 |
Perfect Shuffling for Cycle Efficient Puncturer and Interleaver for Software Defined Radio
|
Jui-Chieh Lin; Minja Hsieh; Ming-Jung Fan-Chiang; Sung-Yen Mao; Chu Yu; Sao-Jie Chen; Yu Hen Hu |
| 國立臺灣海洋大學 |
2010-06 |
Design of a Low Power Viterbi Decoder for Wireless Communication Applications
|
Chih-Jhen Chen; Chu Yu; Mao-Hsu Yen; Pao-Ann Hsiung; Sao-Jie Chen |
| 國立臺灣海洋大學 |
2010 |
A Memoryless Viterbi Decoder for OFDM Systems
|
Chu Yu;Chih-Jhen Chen;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2010 |
Design of a Low Power Viterbi Decoder for Wireless Communication Applications
|
Chih-Jhen Chen;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2009-07 |
Parallel Implementation of Convolution Encoder for Software Defined Radio on DSP Architecture
|
Jui-Chieh Lin;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen;Yu Hen Hu |
| 國立臺灣海洋大學 |
2009-05 |
A 900 MHz to 5.2 GHz Dual-Loop Feedback Multi-band LNA
|
Jia-Wei Lin;Da-Tong Yen;Wei-Yi Hu;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2009-01 |
Design of a High-Speed Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications
|
Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 國立臺灣海洋大學 |
2008 |
A Unified Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications
|
Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen |
| 亞洲大學 |
2002-09-13 |
Verification of Embedded Object-Oriented Software
|
Win-Bin See1; Pao-Ann Hsiung; Trong-Yen Lee; Jih-Ming Fu; Sao-Jie Chen |
| 臺大學術典藏 |
2002 |
TCN: Scalable hierarchical hypercubes
|
Lee, T.-Y.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 國立臺灣海洋大學 |
2001-11 |
A Three-stage One-sided Rearrangeable Polygonal Switching Network
|
Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan |
| 國立臺灣海洋大學 |
2001 |
Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System
|
Mao-Hsu Yen;Sao-Jie Chen;Sanko H. Lan |
| 臺大學術典藏 |
2001 |
Symmetric and programmable multi-chip module for low-power prototyping system
|
SAO-JIE CHEN; Chen, S.-J.; Lan, S.H.; Yen, M.-H. |
| 國立臺灣海洋大學 |
1999-10 |
Symmetric and programmable multi-chip module for rapid prototyping system
|
Mao-Hsu Yen; Sao-Jie Chen; Sanko H. Lan |
| 國立臺灣科技大學 |
1999 |
Symmetric and programmable multi-chip module for rapid prototyping system
|
Mao-Hsu Yen;Sao-Jie Chen;Lan, S.H. |
| 臺大學術典藏 |
1997 |
MOBnet: An extended petri net model for the concurrent object-oriented system-level synthesis of multiprocessor systems
|
Hsiung, P.-A.; Lee, T.-Y.; Chen, S.-J.; SAO-JIE CHEN |
