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Showing items 1-13 of 13 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:45:37Z |
Decoding of CISC instructions in superscalar processors with high issue rate
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Shiu, RM; Chiu, JC; Cheng, SK; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:43:30Z |
Aggressive scheduling for memory accesses of CISC superscalar microprocessors
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Shiu, RM; Hwang, HY; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:41:27Z |
Inverted file compression through document identifier reassignment
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Shieh, WY; Chen, TF; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:40:44Z |
An inverted file cache for fast information retrieval
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Shieh, WY; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:20Z |
Decoding unit with high issue rate for X86 superscalar microprocessors
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Cheng, SK; Shiu, RM; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:27:20Z |
An X86 load/store unit with aggressive scheduling of load/store operations
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Hwang, HY; Shiu, RM; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:26:35Z |
Code compression by register operand dependency
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Lin, K; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:51Z |
A unique-order interpolative code for fast querying and space-efficient indexing in information retrieval systems
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Cheng, CS; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Low-power BIBITS encoding with register relabeling for instruction bus
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Cheng, CT; Chiao, WH; Shann, JJJ; Chung, CP; Chen, WF |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Low-power data address bus encoding method
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Weng, TH; Chiao, WH; Shann, JJJ; Chung, CP; Lu, J |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Low-power branch prediction
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Hu, YC; Chiao, WH; Shann, JJJ; Chung, CP; Chen, WF |
| 國立交通大學 |
2014-12-08T15:17:20Z |
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems
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Cheng, CS; Shann, JJJ; Chung, CP |
| 國立交通大學 |
2014-12-08T15:16:46Z |
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems
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Cheng, CS; Chung, CP; Shann, JJJ |
Showing items 1-13 of 13 (1 Page(s) Totally)
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