臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立中山大學	2000-06	Redunant Constant-Factor Implementation of Multi-dimensional CORDIC and Its Application to Complex SVD	Shen-Fu Hsiao;Chun-Yi Lau;Jean-Marc Delosme
國立中山大學	2000-06	VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking	Shen-Fu Hsiao; Yor-Chin Tai; Kai-Hsiang Chang
國立中山大學	2000-06	Low-Cost Unified Architectures for the Computation of Discrete Trigonometric Transforms	Shen-Fu Hsiao; Wei-Ren Shiue
國立中山大學	2000-05	High-Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Logic	Shen-Fu Hsiao; Jia-Siang Yeh; Da-Yen Chen
國立中山大學	2000-02	Discussions on the CORDIC Processor Using Leading Zero Detectors	Tso-Bing Juang; Shen-Fu Hsiao
國立中山大學	2000-01	An Efficient Synthesizer for Generation of Fast Parallel Multipliers	Shen-Fu Hsiao;Ming-Rong Jiang
國立中山大學	1999-08	A Cost-Efficient and Fully-Pipelinable Linear Architecture for Discrete Cosine Transform	Shen-Fu Hsiao;Wei-Ren Shiue;Jian-Ming Tseng
國立中山大學	1999-08	Direct Implementation of N x N 2-D DCT on a Pipelinable Linear-Array without Intermediate Transpose Memory	Shen-Fu Hsiao; Jian-Ming Tseng
國立中山大學	1999-08	A High-Speed Universal Arithmetic Processor Based on Redundant CORDIC with Constant Scaling Factor and Merged Scaling Operation	Shen-Fu Hsiao; Chun-Yi Lau
國立中山大學	1999-08	A Low Power and Fast CORDIC Processor for Vector Rotation	Tso-Bing Juang; Shen-Fu Hsiao
國立中山大學	1999-08	Direct Implementation of 2-D DCT on a Low-Cost Linear-Array Architecture without Intermediate Transpose Memory	Shen-Fu Hsiao; Jian-Ming Tseng
國立中山大學	1999-06	An Efficient Synthesizer for Generation of Fast Parallel Multipliers	Shen-Fu Hsiao; Ming-Rong Jiang
國立中山大學	1999-06	A Cost-Efficient and Fully-Pipelinable Linear Architecture for Discrete Cosine Transform	Shen-Fu Hsiao; Wei-Ren Shiue; Jian-Ming Tseng
國立中山大學	1999-05	A High-Speed Constant-Factor Redundant CORDIC Processor without Extra Correcting or Scaling Iterations	Shen-Fu Hsiao
國立中山大學	1999-03	New Hardware-Efficient Algorithms and Architectures for Computation of 2-D DCT on Linear Systolic Arrays	Shen-Fu Hsiao; Wei-Ren Shiue
國立中山大學	1999-03	A High-Throughput, Low-Power Architecture and its VLSI Implementation for DFT/IDFT Computation	Wei-Ren Shiue; Shen-Fu Hsiao
國立中山大學	1999	數位運動控制技術之發展與智慧型馬達控制IC之研製---數位馬達控制協同處理器之研製	蕭勝夫; Shen-Fu Hsiao
國立中山大學	1998-12	Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure	Shen-Fu Hsiao;Jen-Yin Chen
國立中山大學	1998-12	Design, Implementation and Error Analysis of Redundant CORDIC Processors for Fast Vector Rotation and Trigonometric Function Evaluation	Shen-Fu Hsiao; Chung-Yi Liu; Jen-Yin Chen
國立中山大學	1998-08	A Hybrid W-Transform-Based Coding and Its VLSI Realization for Image Compression	Shen-Fu Hsiao;Wen-Chen Huang;Chungnan Lee;Cheng-Chung Hsu
國立中山大學	1998-08	High-Performance Multiplier Synthesizer Based on Optimized Partial Product Reduction Tree	Shen-Fu Hsiao; Ming-Rong Jiang
國立中山大學	1998-08	High Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Circuits	Shen-Fu Hsiao; Jia-Siang Yeh
國立中山大學	1998-08	New Hardware-Efficient Architectures for Discrete Fourier Transfor	Shen-Fu Hsiao; Wie-Ren Shiue
國立中山大學	1998-06	Top-Down Logic Design with Pass-Transistor Cells And an Efficient Synthesizer	Shen-Fu Hsiao;Jia-Siang Yeh
國立中山大學	1998-06	A Hybrid W-Transform-Based Coding and Its VLSI Realization for Image Compression	Wen-Chen Huang; Shen-Fu Hsiao; Chung-Nan Lee; Cheng-Chung Hsu

Showing items 61-85 of 114 (5 Page(s) Totally)
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