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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
適用於第三代行動通訊的三模式維特比/渦輪碼解碼器之超大型積體電路設計
|
沈佩玲; Shen, Pei-Ling |
| 臺大學術典藏 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
Showing items 1-7 of 7 (1 Page(s) Totally)
1
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|
