| 國立交通大學 |
2019-04-02T05:59:26Z |
Recursive minimum energy algorithm for image interpolation
|
Liu, PC; Chang, WT; Shen, WZ |
| 國立交通大學 |
2019-04-02T05:59:23Z |
Motion parameter estimation based on the block recursive algorithm with finite word length
|
Liu, PC; Chang, WT; Shen, WZ |
| 國立交通大學 |
2019-04-02T05:58:30Z |
Design and performance evaluation of a distributed knockout switch with input and output buffers
|
Cheng, YJ; Lee, TH; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:48:51Z |
Fault diagnosis of a distributed knockout switch
|
Cheng, YJ; Lee, TH; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:47:21Z |
On circuit clustering for area/delay tradeoff under capacity and pin constraints
|
Huang, JD; Jou, JY; Shen, WZ; Chuang, HH |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A structure-oriented power modeling technique for macrocells
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:59Z |
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
|
Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:44:32Z |
A new method for constructing IP level power model based on power sensitivity
|
Huang, HL; Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
|
Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:55Z |
ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
|
SHEN, WZ; TAO, YH; DUNG, LR |
| 國立交通大學 |
2014-12-08T15:27:54Z |
A CELL-BASED POWER ESTIMATION IN CMOS COMBINATIONAL CIRCUITS
|
LIN, JY; LIU, TC; SHEN, WZ |
| 國立交通大學 |
2014-12-08T15:27:48Z |
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
|
SHEN, WZ; HUANG, JD; CHAO, SM |
| 國立交通大學 |
2014-12-08T15:27:45Z |
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
|
Huang, JD; Joy, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:41Z |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
|
Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:39Z |
CB-Power: A hierarchical cell-based power characterization and estimation environment for static CMOS circuits
|
Shen, WZ; Lin, JY; Lu, JM |
| 國立交通大學 |
2014-12-08T15:27:36Z |
A power modeling and characterization method for the CMOS standard cell library
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:29Z |
A power modeling and characterization method for macrocells using structure information
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:24Z |
Wiener filter for zoom parameter estimation in three-parameter motion model
|
Liu, PC; Shen, WZ; Chang, WT |
| 國立交通大學 |
2014-12-08T15:26:37Z |
Vector compacation for power estimation with grouping and consecutive sampling techniques
|
Hsu, CY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:26:37Z |
Inductance modeling for on-chip interconnects
|
Tu, SW; Shen, WZ; Chang, YW; Chen, TC |
| 國立交通大學 |
2014-12-08T15:06:29Z |
THE OPEN-CIRCUIT VOLTAGE OF BACK-SURFACE-FIELD (BSF) P-N-JUNCTION SOLAR-CELLS IN CONCENTRATED SUNLIGHT
|
WU, CY; SHEN, WZ |
| 國立交通大學 |
2014-12-08T15:06:27Z |
AN ANALYTICAL MODEL FOR HIGH-LOW-EMITTER (HLE) SOLAR-CELLS IN CONCENTRATED SUNLIGHT
|
SHEN, WZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:06:09Z |
MOTA - A MOSFET TIMING SIMULATOR
|
JOU, SJ; JEN, CW; SHEN, WZ; LEE, CL |
| 國立交通大學 |
2014-12-08T15:06:02Z |
SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT
|
JOU, SJ; SHEN, WZ; JEN, CW; LEE, CL |
| 國立交通大學 |
2014-12-08T15:05:43Z |
CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS
|
CHEN, JE; LEE, CL; SHEN, WZ |
