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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"shung cb"的相關文件
顯示項目 21-31 / 31 (共1頁)
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| 國立交通大學 |
2014-12-08T15:05:04Z |
A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS
|
SHUNG, CB; SIEGEL, PH; THAPAR, HK; KARABED, R |
| 國立交通大學 |
2014-12-08T15:04:40Z |
GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM
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CYPHER, R; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:04:34Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:32Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:17Z |
REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM
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THAPAR, HK; SHUNG, CB; RAE, JW; KARABED, R; SIEGEL, PH |
| 國立交通大學 |
2014-12-08T15:03:15Z |
SHARED BUFFER ATM SWITCH WITH DOUBLY LINKED LISTS
|
LIN, YF; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:02:30Z |
Multiple-training bi-directional adaptive equalizers for TDMA digital cellular systems
|
Chen, MJ; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:20Z |
Technology mapping for FPGAs with composite logic block architectures
|
Chuang, HH; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:14Z |
A queue manager chip for shared buffer ATM switches
|
Lin, YS; Huang, HC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:03Z |
Special issue on applications of low power design - Preface
|
Shung, CB; Yan, RH; Kubo, M |
| 國立交通大學 |
2014-12-08T15:01:26Z |
Event-driven power estimation of CMOS circuits
|
Tsai, WC; Shung, CB |
顯示項目 21-31 / 31 (共1頁)
1
每頁顯示[10|25|50]項目
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