|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"shung cb"
Showing items 16-31 of 31 (1 Page(s) Totally)
1
View [10|25|50] records per page
| 國立交通大學 |
2014-12-08T15:27:33Z |
Queue management for shared buffer and shared multi-buffer ATM switches
|
Lin, YS; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:27Z |
VLSI design of a priority arbitrator for shared buffer ATM switches
|
Lin, YS; Yang, SC; Fang, SJ; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:26Z |
Reactive bandwidth arbitration for priority and multicasting control in ATM switching
|
Fang, SJ; Lin, YS; Yang, SC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:17Z |
A (208,192;8) Reed-Solomon decoder for DVD application
|
Chang, HC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:05:17Z |
AN INTEGRATED CAD SYSTEM FOR ALGORITHM-SPECIFIC IC DESIGN
|
SHUNG, CB; JAIN, R; RIMEY, K; WANG, E; SRIVASTAVA, MB; RICHARDS, BC; LETTANG, E; AZIM, SK; THON, L; HILFINGER, PN; RABAEY, JM; BRODERSEN, RW |
| 國立交通大學 |
2014-12-08T15:05:04Z |
A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS
|
SHUNG, CB; SIEGEL, PH; THAPAR, HK; KARABED, R |
| 國立交通大學 |
2014-12-08T15:04:40Z |
GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM
|
CYPHER, R; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:04:34Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:32Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:17Z |
REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM
|
THAPAR, HK; SHUNG, CB; RAE, JW; KARABED, R; SIEGEL, PH |
| 國立交通大學 |
2014-12-08T15:03:15Z |
SHARED BUFFER ATM SWITCH WITH DOUBLY LINKED LISTS
|
LIN, YF; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:02:30Z |
Multiple-training bi-directional adaptive equalizers for TDMA digital cellular systems
|
Chen, MJ; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:20Z |
Technology mapping for FPGAs with composite logic block architectures
|
Chuang, HH; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:14Z |
A queue manager chip for shared buffer ATM switches
|
Lin, YS; Huang, HC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:02:03Z |
Special issue on applications of low power design - Preface
|
Shung, CB; Yan, RH; Kubo, M |
| 國立交通大學 |
2014-12-08T15:01:26Z |
Event-driven power estimation of CMOS circuits
|
Tsai, WC; Shung, CB |
Showing items 16-31 of 31 (1 Page(s) Totally)
1
View [10|25|50] records per page
|
