臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 21-37 of 37 (1 Page(s) Totally)
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Institution	Date	Title	Author
南台科技大學	1999-02	An Efficient Search Algorithm for Block-Matching Motion Estimation	Pei-Yin Chen; Jer Min Jou; Shung-Chih Chen
南台科技大學	1998-05	Fast Delay-Dependent Power Estimation of Large Combinational Circuits	Jer Min Jou; Shung-Chih Chen; Chih-Liang Wang; 陳順智
南台科技大學	1998-02	Efficient Diagnostic Fault Simulation Algorithm for Combinational Circuits	陳順智;Shung-Chih Chen
南台科技大學	1997-11	Serial Diagnostic Fault Simulation for Synchronous Sequential Circuits	Shung-Chih Chen; Jer-Min Jou;陳順智
南台科技大學	1997-03	Diagnostic Fault Simulation for Synchronous Sequential Circuits	Shung-Chih Chen; Jer Min Jou;陳順智
南台科技大學	1996-08	Hierarchical Power Estimation of Digital Circuits	Jer Min Jou; R, -H, Hung; Shung-Chih Chen
南台科技大學	1996-04	A Fast Combinational Fault Simulation Algorithm	Shung-Chih Chen; 陳順智
南台科技大學	1995-05	Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning	Jer Min Jou; Shung-Chih Chen; 陳順智
南台科技大學	1994-06	A New Fault Simulator for Large Synchronous Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 陳順智
南台科技大學	1994-06	An Improved Diagnostic Fault Simulation for Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 陳順智
南台科技大學	1994-06	Efficient diagnostic fault simulation for sequential circuits	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1994-05	A Super Fast and Memory Efficient Diagnostic Simulation Algorithm for Combinational Circuits	Jer Min Jou; Shung-Chih Chen; Ren-Der Chen; 陳順智
南台科技大學	1994-04	A Fast and Memory-Efficient Diagnostic Fault Simulation for Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1993-05	PARCRIPT: a very fast combinational fault simulator	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1992-03	An Efficient VHDL Simulator with Two-Simulation-Run Ability	Jer Min Jou; Shung-Chih Chen
南台科技大學	1992-01	MASS: An Integrated Approach to High Level Synthesis	Jer Min Jou; S. R. Kuang; Shung-Chih Chen
南台科技大學	1991-12	An Efficient Mixed-level VHDL Simulator with Robust Debugging Capability	Jer Min Jou; Shung-Chih Chen

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